SLLSEA9B February 2012 – August 2015 SN75DP126
PRODUCTION DATA.
The SN75DP126 compensates for PCB related frequency loss and switching related loss to provide the optimum electrical performance from source to SINK. THE DP++ main link signal inputs feature configurable equalizers with selectable boost settings.
The SN75DP126 switches one dual-mode Displayport (DP++) input to one Dual-mode Displayport (DP++) sink output or one HDMI/DVI sink outpuT. The HDMI/DVI output has a built in level translator compliant with DVI 1.0 and HDMI 1.4A standard TMDS signaling, and is specified up to a maximum data rate of 3.5GBPS, supporting resolutions greater than 1920 × 1440 and HDTV deep color at 1080P. An integrated DP-HDMI adaptor ID buffer can be accessed when the HDMI/DVI sink is selected to indicate support for HDMI signaling.
The SN75DP126 EN input gives control over the device reset and to place the device into Shutdown mode. When EN is low, all DPCD and local I2C registers are reset to their default values, and all Main Link lanes are disabled.
It is critical to reset the digital logic of the SN75DP126 after the VCC supply (and VDD supply for SN75DP126DS) is stable (that is, the power supply has reached the minimum recommended operating voltage). To reset the digital logic, transition the EN input from a low level to a high level. This method is shown in Figure 22. A system may provide a control signal to the EN signal that transitions low to high after the power supply is (or supplies are) stable. An alternate implementation is to use an external capacitor connected between EN and GND to allow delaying the EN signal during power up, as shown in Figure 23.
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When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC (and VDD when applicable) supply, where a slower ramp-up results in a larger value external capacitor.Refer to the latest reference schematic for the SN75DP126 device and/or consider approximately 200nF capacitor as a reasonable first estimate for the size of the external capacitor.
When implementing an EN input from an active controller, it is recommended to use an open drain driver if the EN input is driven. This protects the EN input from damage of an input voltage greater than VDD_DREG (or VDD).
The SN75DP126 drives the source-side Hot Plug Detect (HPD_SRC) signal output high to indicate to the GPU or graphics source that at least one sink has been detected and selected for connectivity; when no sink is selected the HPD_SRC is driven low. A high-level DP_HPD_SNK input indicates a DisplayPort sink device is connected, and a high-level TMDS_HPD_SNK input indicates a HDMI/DVI sink device is connected.
When DP_HPD_SNK is high, the DisplayPort sink is selected if the TMDS_HPD_SNK input is low. When TMDS_HPD_SNK is high, the HDMI/DVI sink is selected if the DP_HPD_SNK input is low. If both DP_HPD_SNK and TMDS_HPD_SNK inputs are high, then the PRIORITY input determines which sink is selected.
When the DisplayPort sink is selected, the CAD_SNK input indicates whether a DP sink (CAD_SNK = low) or a TMDS sink (CAD_SNK = high) is connected. The level of CAD_SNK is passed to the CAD_SRC output when the DisplayPort sink is selected. When the HDMI/DVI sink is selected, the CAD_SRC output is driven high regardless of the value input on CAD_SRC.
A sink is determined to be disconnected when the corresponding HPD_SNK input goes low for a duration of tT(HPD). When switching from one sink to the other based on the PRIORITY selection, that is, both sinks are connected and either PRIORITY has changed or the sink with higher PRIORITY was connected after the sink with lower PRIORITY, the SN75DP126 asserts HPD_SRC for a duration at least tT(HPD) before the switchover connection is established.
Through the local I2C interface it is possible to force the device to ignore DP_HPD_SNK, TMDS_HPD_SNK, and CAD_SNK, and control HPD_SRC and CAD_SRC directly.
When the EN pin is de-asserted (device is in power down mode), the HPD path from DP_HPD_SNK and/or TMDS_HPD_SNK to HPD_SRC is not reset. As a result, the source may need to retrain the link once EN is asserted (device is in active mode).
See Figure 10 and Table 1 for more information about the HPD and CAD functions.
The SN75DP126 provides an output-voltage select (OVS) control for the source side buffers on the DDC I2C lines. When the sink side is driven low, the corresponding source side driver turns on and drives the source side down to a low-level output voltage, VOL. The value of VOL and VIL on the source side of the SN75DP126 depends on setting of the OVS pin. VOL is always higher than VIL on the source side to prevent lockup of the buffers on the DDC I2C lines. When the sink side is pulled up, the source side driver turns off and the sink side pin is high-impedance.
When the source side is driven below VIL by an external I2C driver, both the sink and source side drivers are turned on. The sink side driver drives the sink side to near 0V, and the source side driver is on, but is overridden by the external I2C driver. When the source side is released by the external I2C driver, the source side driver is still on, so the source side is only able to rise to VOL. However, the sink side driver turns off because the source side is above the VIL threshold. If no external I2C driver is keeping the sink side low, the sink side rises causing the source side driver to turn off. See Figure 13 and Figure 14 for more information.
It is important that any external I2C driver on the source side is able to drive the bus below VIL to achieve full operation. If the source side cannot be driven below VIL, the sink side driver may not recognize and transmit the low value to the sink side.
The SN75DP126 connectivity between source-side AUX and DDC channels and the sink-side AUX and DDC channels is described in Table 3. Refer to the BLOCK DIAGRAM for more information about the AUX and DDC switches, buffers, and logic elements represented in Table 1.
Note that the DDC interface incorporates 60kΩ pull-up resistors on SDA_SRC and SCL_SRC which are enabled when CAD_SRC is driven high, and disabled (turned off) when CAD_SRC is driven low.
INPUTS | OUTPUTS AND CONTROLS | COMMENTS | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TMDS_HPD_SNK | DP_HPD_SNK | PRIORITY (1) | CAD_SNK | CAD_SRC (2) (Source-Side Output) | AUX_SRC SWITCH | DDC_SRC SWITCH | DP AUX_SNK SWITCH | HDMI/DVI DDC LEVEL- | SHIFTI I/O BUFFERS | AUX MONITOR (Link Training) | 14DP-HDMI ADAPTOR ID12 | (1580h/81h DDC Buffer) | |
0 | 0 | X | 0 | 0(3) | OFF | OFF | OFF | OFF | OFF | OFF | no sink selected; low power mode | ||
1 | 1(3) | ||||||||||||
0 | 1 | X | 0 | 0 | ON | OFF | ON | OFF | ON | OFF | DisplayPort sink selected; operating in DP mode; AUX_SNK connects to AUX_SRC and Link Training enabled | ||
1 | 1 | 0 | |||||||||||
0 | 1 | X | 1 | 1 | OFF | ON | ON | OFF | OFF | OFF | DisplayPort sink selected; operating in TMDS mode; AUX_SNK connects to source-side DDC (SCL/SDA_SRC) | ||
1 | 1 | 0 | |||||||||||
1 | 0 | X | X | 1 | OFF | ON | OFF | ON | OFF | ON | HDMI/DVI sink selected; connect the source-side DDC to sink-side DDC; enable the DP-HDMI Adaptor ID accessed via DDC addresses 80h/81h | ||
1 | 1 | 1 |
A variety of EQ settings are available through external pin configuration to accommodate for different PCB loss and GPU settings. The I2C interface is utilized to fully customize EQ configuration, lane-by-lane, beyond the input pin configuration options, as described in Table 2.
INPUTS | EQ SETTINGS | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
EQ_I2C_ENABLE(1) | (Register 05.7) | I2C_CTL_EN | (3-Level Input) | SCL_CTL/EQ | (3-Level Input) | LINK_TRAINING_ENABLE(1) | (Register 04.2) | DISPLAYPORT SIGNAL MODE(2)(3)
SOURCE LANES IN[3:0] |
TMDS SIGNAL MODE(4)
(TMDS DATA) SOURCE LANES IN[2:0] |
TMDS SIGNAL MODE(4)
(TMDS CLOCK) SOURCE LANE IN[3] |
0 | ≤ VIL | ≤ VIL | 1 | AEQ(L0) = 8 dB at 2.7 GHz AEQ(L1) = 6 dB at 2.7 GHz AEQ(L2) = 3.5 dB at 2.7 GHz AEQ(L3) = 0 dB at 2.7 GHz |
6 dB at 2.7 GHz | 3 dB at 1.35 GHz | ||||
0 | 6 dB at 2.7 GHz | |||||||||
VIM | X | 6 dB at 2.7 GHz | 6 dB at 2.7 GHz | 3 dB at 1.35 GHz | ||||||
≥ VIH | 13 dB at 2.7GHz | 13 dB at 2.7 GHz | 3 dB at 1.35 GHz | |||||||
VIM | X | 1 | AEQ(L0) = 15 dB at 2.7 GHz AEQ(L1) = 13 dB at 2.7 GHz AEQ(L2) = 10 dB at 2.7 GHz AEQ(L3) = 6 dB at 2.7 GHz |
13 dB at 2.7 GHz | 3 dB at 1.35 GHz | |||||
0 | 13 dB at 2.7 GHz | |||||||||
≥ VIH | X | 18 dB at 2.7 GHz | 18 dB at 2.7 GHz | 3 dB at 1.35 GHz | ||||||
1 | VIM or ≥ VIH |
X | 1 | AEQ(Lx) = 0 dB at 2.7 GHz (default) EQ settings for each link training level can be selected via local I2C |
0 dB at 2.7 GHz (default) EQ settings selected via local I2C, training level L1 (AEQ_L1_LANEx_SET registers) |
3 dB at 1.35 GHz | ||||
0 | 0 dB at 2.7 GHz (default) EQ settings selected via local I2C; training level L1 (AEQ_L1_LANEx_SET registers) |
0 dB at 2.7 GHz (default) EQ settings selected via local I2C; training level L1 (AEQ_L1_LANEx_SET registers) |
3 dB at 1.35 GHz |
The SN75DP126 includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by the VESA DisplayPort Interoperability Guidelines Version 1.1a, accessible by standard I2C protocols through the DDC interface when the HDMI/DVI sink is selected. The DP-HDMI adapter buffer is accessed at target addresses 80h (Write) and 81h (Read).
The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII characters as illustrated in Table 3, and supports the Write command procedures (accessed at target address 80h) to select the sub-address, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor Checklist Version 1.0 section 2.3.
Address | 0x00 | 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 |
Data | 44 | 50 | 2D | 48 | 44 | 4D | 49 | 20 | 41 | 44 | 41 | 50 | 54 | 4F | 52 | 04 | FF |
The SN75DP126 supports graphics processors with unified AUX/DDC configurations, where the source AUX channel is multiplexed with the source DDC channel, as illustrated in Figure 24.
Graphics processors with separate AUX and DDC channels (ie. non-unified) are also supported, where the separate channels are directly routed to the separate channels on the SN75DP126, maintaining the AC coupling on the AUX channel. In the non-unified configuration, it is recommended to implement 2-kΩ pull-up resistors on the source-side DDC channel. See Figure 25.
Graphics processors with separate AUX and DDC channels (ie. non-unified) are also supported, where the separate channels are directly routed to the separate channels on the SN75DP126, maintaining the AC coupling on the AUX channel. In the non-unified configuration, it is recommended to implement 2-kΩ pull-up resistors on the source-side DDC channel. See Figure 25.
MODE | CHARACTERISTICS | CONDITIONS |
---|---|---|
Shutdown Mode | Least amount of power consumption (most circuitry turned off); HPD_SRC output is asserted if either DP_HPD_SNK or TMDS_HPD_SNK are input active (high); all other outputs are high-impedance; all other inputs are ignored; the local I2C interface is inactive; in this state all local I2C registers and DPCD registers are set to default values. | EN is low |
Standby Mode | Main Link outputs are disabled; the local I2C interface is active; in this state, the HPD_SRC (and CAD_SRC) outputs are driven low for at least tT(HPD) to indicate no sink connectivity to the source; the SN75DP126 passes through this state when transitioning from one active sink to the other for reasons of PRIORITY selection, where the HPD_SRC de-assertion for at least tT(HPD) communicates the sink plug event to the source. | EN is high; Either no sink is connected, or both sinks are connected and PRIORITY causes a transition from one sink to the other sink |
DisplayPort Active Mode | The DisplayPort sink is selected and data transfer is enabled (normal operation); the Main Link output is either TMDS mode (CAD_SNK = 1) or DisplayPort mode (CAD_SNK = 0). | EN is high; DP_HPD_SNK is high, but after entering this state, DP_HPD_SNK can be low for less than tT(HPD) (for example, sink interrupt request to source); If both TMDS_HPD_SNK and DP_HPD_SNK are high, then a low input on PRIORITY causes the DisplayPort sink selection |
In TMDS mode, the DDC source-side channel (SCL/SDA_SRC) is connected to the sink DDC channel (AUX_SNK p/n) through a low-resistance circuit; and the CAD_SRC output is driven high. In TMDS mode the output signal swing is 600 mVpp unless this setting is adjusted through local I2C interface programming; the Main Link input equalizer settings depend on device control inputs and local I2C settings. | ||
In DisplayPort mode the AUX source-side channel is connected to the sink AUX channel through a low-resistance circuit; and the CAD_SRC output is driven low. The AUX monitor is active for Link Training, which automatically updates the DPCD registers to enable the Main Link outputs (this Link Training operation may be de-activated and overridden by direct local I2C programming); transactions other than Link Training and D3 power management commands are ignored on the AUX interface; the Main Link output signal conditioning (pre-emphasis and VOD) and Main Link input equalizer settings depend on the Link Training, device control inputs, and local I2C settings. | ||
D3 Power Down Mode | DisplayPort D3 low-power mode; DisplayPort sink Main Link outputs are disabled; local I2C interface is active; AUX monitor is active. | EN is high; DisplayPort sink is selected, and operating in DisplayPort mode (CAD_SNK = 0); “Enter D3” AUX command has been performed |
HDMI/DVI Active Mode | The HDMI/DVI sink is selected and data transfer is enabled (normal operation); the HDMI/DVI Main Link output (TMDS signaling) is enabled. | EN is high; TMDS_HPD_SNK is high; If both TMDS_HPD_SNK and DP_HPD_SNK are high, then a high input on PRIORITY causes the HDMI/DVI sink selection |
The DDC source-side channel (SCL/SDA_SRC) is connected to the HDMI/DVI sink DDC channel (SCL/SDA_SNK) through an I2C buffer that separates the capacitive load between the source and sink; the DP-HDMI Adapter ID buffer containing a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII characters at DDC (I2C target) addresses 80h(Write)/81h(Read) per the VESA DisplayPort Interoperability Guidelines Version 1.1a | ||
The HDMI/DVI Main Link output signal conditioning (pre-emphasis and VOD) and Main Link input equalizer settings depend on the device control inputs and local I2C settings. | ||
Output Disable Mode | When low-signal levels on the source Main Link input are sensed (a squelch event) when in either sink-side is selected for active mode, a transition to this state occurs and the sink-side Main Link outputs are disabled; when the source Main Link input signal levels are above a pre-determined threshold, a transition back to the appropriate active mode occurs. | EN is high; DPCD register 101h or 103h entry is invalid |
Other than a disabled Main Link output, this state characteristics are identical to the active state from where the transition occurred. | ||
A transition to this state may occur from DisplayPort Active Mode, D3 Power Down Mode, or Compliance Test Mode when DPCD writes (from the local I2C or the AUX channel) update the DPCD 101h or 103h registers with invalid values; this action causes the DP sink to issue an interrupt and re-train the link. | ||
Compliance Test Mode | Through local I2C registers the device can be forced into ignoring TMDS_HPD_SNK, DP_HPD_SNK, and CAD_SNK; HPD_SRC and CAD_SRC outputs are programmed through local I2C registers (default output low); all other configurations (such as output signal conditioning and EQ settings) are programmable through the local I2C registers in this state. | EN is high; Local I2C programming selects the this mode |
The SN75DP126 can monitor the auxiliary interface access to DisplayPort Configuration Data (DPCD) registers during Link Training in DisplayPort mode, to select the output voltage swing VOD, output pre-emphasis, and the EQ setting of the Main Link. The AUX monitor for SN75DP126 supports Link Training in 1-Mbps Manchester mode, and is disabled during TMDS modes of operation.
The DPCD registers monitored by SN75DP126 are listed below. Bit fields not listed are reserved and values written to reserved fields are ignored.
ADDRESS | NAME | DESCRIPTION |
---|---|---|
00100h | LINK_BW_SET | Bits 7:0 = Link Bandwidth Setting Write Values: 06h – 1.62 Gbps per lane 0Ah – 2.7 Gbps per lane (default) 14h – 5.4 Gbps per lane Note: any other value is reserved; the SN75DP126 will revert to 5.4 Gbps operation when any other value is written Read Values: 00h – 1.62 Gbps per lane 01h – 2.7 Gbps per lane (default) 02h – 5.4 Gbps per lane |
00101h | LANE_COUNT_SET | Bits 4:0 = Lane Count Write Values: 0h – All lanes disabled (default) 1h – One lane enabled 2h – Two lanes enabled 4h – Four lanes enabled Note: any other value is invalid and disables all Main Link output lanes Read Values: 0h – All lanes disabled (default) 1h – One lane enabled 3h – Two lanes enabled Fh – Four lanes enabled |
00103h | TRAINING_LANE0_SET | Write Values: Bits 1:0 = Output Voltage VOD Level 00 – Voltage swing level 0 (default) 01 – Voltage swing level 1 10 – Voltage swing level 2 11 – Voltage swing level 3 Bits 4:3 = Pre-emphasis Level 00 – Pre-emphasis level 0 (default) 01 – Pre-emphasis level 1 10 – Pre-emphasis level 2 11 – Pre-emphasis level 3 Note: the following combinations are not allowed for bits [1:0]/[4:3]: 01/11, 10/10, 10/11, 11/01, 11/10, 11/11; setting to any of these invalid combinations disables all Main Link lanes until the register value is changed back to a valid entry Read Values: Bits 1:0 = Output Voltage VOD Level 00 – Voltage swing level 0 (default) 01 – Voltage swing level 1 10 – Voltage swing level 2 11 – Voltage swing level 3 Bits 3:2 = Pre-emphasis Level 00 – Pre-emphasis level 0 (default) 01 – Pre-emphasis level 110 – Pre-emphasis level 2 11 – Pre-emphasis level 3 |
00104h | TRAINING_LANE1_SET | Sets the VOD and pre-emphasis levels for lane 1 |
00105h | TRAINING_LANE2_SET | Sets the VOD and pre-emphasis levels for lane 2 |
00106h | TRAINING_LANE3_SET | Sets the VOD and pre-emphasis levels for lane 3 |
0010F | TRAINING_LANE0_1_SET2 | Write Values: Bits 1:0 = Lane 0 Post Cursor 2 00 – IN0 expects post cursor2 level 0; OUT0 transmits at post cursor 2 level 0 01 – IN0 expects post cursor2 level 1; OUT0 transmits at post cursor 2 level 0 10 – IN0 expects post cursor2 level 2; OUT0 transmits at post cursor 2 level 0 11 – IN0 expects post cursor2 level 3; OUT0 transmits at post cursor 2 level 0 Bits 5:4 = Lane 1 Post Cursor 2 00 – IN1 expects post cursor2 level 0; OUT1 transmits at post cursor 2 level 0 01 – IN1 expects post cursor2 level 1; OUT1 transmits at post cursor 2 level 0 10 – IN1 expects post cursor2 level 2; OUT1 transmits at post cursor 2 level 0 11 – IN1 expects post cursor2 level 3; OUT1 transmits at post cursor 2 level 0 Read Values: Bits 1:0 = Lane 0 Post Cursor 2 00 – IN0 expects post cursor2 level 0; OUT0 transmits at post cursor 2 level 0 01 – IN0 expects post cursor2 level 1; OUT0 transmits at post cursor 2 level 0 10 – IN0 expects post cursor2 level 2; OUT0 transmits at post cursor 2 level 0 11 – IN0 expects post cursor2 level 3; OUT0 transmits at post cursor 2 level 0 Bits 3:2 = Lane 1 Post Cursor 2 00 – IN1 expects post cursor2 level 0; OUT1 transmits at post cursor 2 level 0 01 – IN1 expects post cursor2 level 1; OUT1 transmits at post cursor 2 level 0 10 – IN1 expects post cursor2 level 2; OUT1 transmits at post cursor 2 level 0 11 – IN1 expects post cursor2 level 3; OUT1 transmits at post cursor 2 level 0 |
0110F | TRAINING_LANE2_3_SET2 | Bit definition identical to that of TRAINING_LANE_0_1_SET2 but for lanes 2 (IN2/OUT2) and lane 3 (IN3/OUT3) |
00600h | SET_POWER | Bits 1:0 = Power Mode Write Values: 01 – Normal mode (default) 10 – Power down mode; D3 Standby Mode The Main Link and all analog circuits are shut down and the AUX channel is monitored during the D3 Standby Mode. The device exits D3 Standby Mode by access to this register, when CAD_SNK goes high, or if DP_HPD_SNK goes low for longer than tT(HPD), which indicates that the DP sink was disconnected, or that the PRIORITY control has selected the HDMI/DVI sink. Note: setting the register to the invalid combination 0600h[1:0] = 00 or 11 is ignored by the device and the device remains in normal mode Read Values: 00 – Normal mode (default) 01 – Power-down mode; D3 Standby Mode |
The SN75DP126 local I2C interface is enabled when EN is input high, and the I2C_CTL_EN control input is not input low. The SCL_CTL and SDA_CTL terminals are used for I2C clock and I2C data respectively. The SN75DP126 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the standard mode transfer up to 100 kbps.
The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN75DP126 is factory preset to 010110x with the least significant bit being determined by the I2C_CTL_EN 3-level control input. Table 6 clarifies the SN75DP126 target address.
SN75DP126 I2C TARGET ADDRESS | |||||||
---|---|---|---|---|---|---|---|
BIT 7 (MSB) | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 (W/R) |
0 | 1 | 0 | 1 | 1 | 0 | X | 0/1 |
I2C_CTL_EN = Low : | Local I2C interface is disabled. |
I2C_CTL_EN = Between VIL and VIH: | X = 0, Address Cycle is 0x58 (Write) and 0x59 (Read). |
I2C_CTL_EN = High: | X = 1, Address Cycle is 0x5A (Write) and 0x5B (Read). |
The following procedure is followed to write to the SN75DP126 I2C registers:
The following procedure is followed to read the SN75DP126 I2C registers.
Note that no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation.
Refer to Table 7 for SN75DP126 local I2C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored.
ADDRESS | BIT(S) | DESCRIPTION | ACCESS | |
---|---|---|---|---|
01h | 3:2 | SINK_PORT_SELECT | RW | |
00 – DP_HPD_SNK and TMDS_HPD_SNK select the sink; when both are asserted, the PRIORITY control input is used where PRIORITY = LOW selects the DisplayPort sink (default) | ||||
01 – DP_HPD_SNK and TMDS_HPD_SNK select the sink; when both are asserted, the PRIORITY control input is used where PRIORITY = LOW selects the HDMI/DVI sink | ||||
10 – Force DisplayPort sink selection regardless of device HPD and control inputs | ||||
11 – Force HDMI/DVI sink selection regardless of device HPD and control inputs | ||||
1 | FORCE_HPD_SRC | RW | ||
0 – Enter Standby mode when DP_HPD_SNK and TMDS_HPD_SNK are input low, and drive HPD_SRC high when DP_HPD_SNK or TMDS_HPD_SNK are input high (default) | ||||
1 – Drive HPD_SRC output high regardless of DP_HPD_SNK and TMDS_HPD_SNK inputs | ||||
0 | FORCE_SHUTDOWN_MODE | RW | ||
0 – SN75DP126 is forced to Shutdown mode | ||||
1 – Shutdown mode is determined by EN input, normal operation (default) | ||||
02h | 7:0 | TI_TEST. This field defaults to zero value, and should not be modified. | RW | |
03h | 5:4 | SQUELCH_SENSITIVITY. Input Main Link squelch sensitivity is selected by this field, and determines the transitions to and from the Output Disable mode. | RW | |
00 – Main Link IN0p/n squelch detection threshold set to 60 mVpp | ||||
01 – Main Link IN0p/n squelch detection threshold set to 115 mVpp (default) | ||||
10 – Main Link IN0p/n squelch detection threshold set to 160 mVpp | ||||
11 – Main Link IN0p/n squelch detection threshold set to 200 mVpp | ||||
3 | SQUELCH_ENABLE | RW | ||
0 – Main Link IN0p/n squelch detection enabled (default) | ||||
1 – Main Link IN0p/n squelch detection disabled | ||||
04h | 3 | TI_TEST. This field defaults to zero value, and should not be modified. | RW | |
2 | LINK_TRAINING_ENABLE | RW | ||
0 – DisplayPort sink Link Training is disabled. VOD and Pre-emphasis are configured through the I2C register interface; the EQ is fixed when this bit is zero. | ||||
1 – DisplayPort sink Link Training is enabled (default) | ||||
1 | Reserved - Do not change this value | R/W | ||
05h | 7 | EQ_I2C_ENABLE | RW | |
0 – EQ settings controlled by device inputs only (default) | ||||
1 – EQ settings controlled by I2C register settings | ||||
6:4 | AEQ_L0_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. | RW | ||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L1_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following non-AEQ modes: | RW | ||
MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled | ||||
MM ● I2C_EQ_ENABLE is set and the TMDS sink is selected. | ||||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
06h | 6:4 | AEQ_L2_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. | RW | |
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L3_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. | RW | ||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
07h | 6:4 | AEQ_L0_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. | RW | |
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L1_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following non-AEQ modes: | RW | ||
MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled | ||||
MM ● I2C_EQ_ENABLE is set and the TMDS sink is selected. | ||||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
08h | 6:4 | AEQ_L2_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. | RW | |
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L3_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. | RW | ||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
09h | 6:4 | AEQ_L0_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. | RW | |
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L1_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following non-AEQ modes: | RW | ||
MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled | ||||
MM ● I2C_EQ_ENABLE is set and the TMDS sink is selected. | ||||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
0Ah | 6:4 | AEQ_L2_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. | RW | |
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L3_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. | RW | ||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
0Bh | 6:4 | AEQ_L0_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. | RW | |
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L1_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following non-AEQ mode: | RW | ||
MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled | ||||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
0Ch | 6:4 | AEQ_L2_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. | RW | |
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
2:0 | AEQ_L3_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. | RW | ||
000 – 0 dB EQ gain (default) | 100 – 5 dB (HBR); 10 dB (HBR2) | |||
001 – 1.5 dB (HBR); 3.5 dB (HBR2) | 101 – 6 dB (HBR); 13 dB (HBR2) | |||
010 – 3 dB (HBR); 6 dB (HBR2) | 110 – 7 dB (HBR); 15 dB (HBR2) | |||
011 – 4 dB (HBR); 8 dB (HBR2) | 111 – 9 dB (HBR); 18 dB (HBR2) | |||
15h | 4:3 | DP_BOOST. Controls the output pre-emphasis amplitude when the DisplayPort sink is selected; allows to reduce or increase all pre-emphasis settings by ~10%. Setting this field will impact VOD when pre-emphasis is disabled. | RW | |
This setting also impacts the output in TMDS mode for the DisplayPort sink connection when the DisplayPort sink CAD_SNK input is high. | ||||
00 – Pre-emphasis reduced by ~10%; VOD reduced by 10% if pre-emphasis is disabled. | ||||
01 – Pre-emphasis nominal (default) | ||||
10 – Pre-emphasis increased by ~10%; VOD increased by 10% if pre-emphasis is disabled. | ||||
11 – Reserved | ||||
2 | DP_TMDS_VOD. Sets the target output swing in TMDS mode when the DisplayPort sink is selected, where CAD_SNK input is high. | RW | ||
0 – Low TMDS output swing for DisplayPort sink channel (default) | ||||
1 – High TMDS output swing for DisplayPort sink channel | ||||
1:0 | DP_TMDS_VPRE. Controls the output pre-emphasis in TMDS mode when the DisplayPort sink is selected, where CAD_SNK input is high. | RW | ||
00 – No TMDS pre-emphasis for DisplayPort sink channel (default) | ||||
01 – Low TMDS pre-emphasis for DisplayPort sink channel | ||||
10 – High TMDS pre-emphasis for DisplayPort sink channel | ||||
11 – Reserved | ||||
17h | 3 | DP_HPD_TEST_MODE | ||
0 – Normal HPD operating mode. (default) | RW | |||
1 – DisplayPort sink compliance test mode. DP_HPD_SNK is pulled high internally, the TMDS_HPD_SNK is pulled low internally, and the HPD_SRC output is driven high and the Main Link is activated depending on the squelch setting. | ||||
1 | CAD_OUTPUT_INVERT | RW | ||
0 – CAD_SRC output high means TMDS cable adapter detected when the DisplayPort sink is selected (default) | ||||
1 – CAD_SRC output low means TMDS cable adapter detected when the DisplayPort sink is selected | ||||
0 | CAD_TEST_MODE | |||
0 – Normal CAD mode. CAD_SRC reflects the status of CAD_SNK, based on the value of CAD_OUTPUT_INVERT, when the DisplayPort sink is selected (default) | ||||
1 – Test mode. CAD_SRC indicates TMDS mode when the DisplayPort sink is selected, depending on the value of CAD_OUTPUT_INVERT; CAD_SNK input is ignored. This mode allows execution of certain tests on SN75DP126 without a connected TMDS display sink. | ||||
18h | 3:2 | HDMI/DVI_PRE | RW | |
00 – 0 dB Pre-emphasis applied to the HDMI/DVI sink TMDS output | ||||
01 – Reserved | ||||
10 – Reserved | ||||
11 – 2 dB Pre-emphasis applied to the HDMI/DVI sink TMDS output | ||||
19h – 1Ah | 7:0 | TI_TEST. These registers shall not be modified. | RW | |
1Bh | 7 | I2C_SOFT_RESET. Writing a one to this register resets all I2C registers to default values. Writing a zero to this register has no effect. Reads from this register return zero. | WO | |
6 | DPCD_RESET. Writing a one to this register resets the DPCD register bits (corresponding to DPCD addresses 103h – 10Fh). Writing a zero to this register has no effect. Reads from this register return zero. | WO | ||
1Ch | 3:0 | DPCD_ADDR_HIGH. This value maps to bits 19:16 of the 20-bit DPCD register address accessed through the DPCD_DATA register. | RW | |
1Dh | 7:0 | DPCD_ADDR_MID. This value maps to bits 15:8 of the 20-bit DPCD register address accessed through the DPCD_DATA register. | RW | |
1Eh | 7:0 | DPCD_ADDR_LOW. This value maps to bits 7:0 of the 20-bit DPCD register address accessed through the DPCD_DATA register. | RW | |
1Fh | 7:0 | DPCD_DATA. This register contains the data to write into or read from the DPCD register addressed by DPCD_ADDR_HIGH, DPCD_ADDR_MID, and DPCD_ADDR_LOW. | RW | |
20h | 7:1 | DEV_ID_REV. This field identifies the device and revision. | RO | |
0000000 – SN75DP126 Revision 0 | ||||
0 | BIT_INVERT. The value read from this field is the inverse of that written. | RW | ||
Default read value is ’1’. | ||||
21h | 7:0 | TI_TEST. These registers shall not be modified. | RW | |
22h – 27h | 7:0 | TI_TEST_RESERVED. These read only registers are reserved for test; writes are ignored. | RO |