SLLSE57E April   2011  – March 2015 SN75DP130

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Dissipation
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Signal
      2. 9.3.2 Hot Plug Detect and Cable Adapter Detect
      3. 9.3.3 AUX and DDC Configuration
      4. 9.3.4 Main Link Configuration
      5. 9.3.5 Link Training and DPCD
      6. 9.3.6 Equalization
      7. 9.3.7 Configurable Outputs
      8. 9.3.8 Squelch
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 I2C Interface Overview
    6. 9.6 Register Maps
      1. 9.6.1 SN75DP130 Local I2C Control and Status Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Logic I2C Interface
        2. 10.2.2.2 CAD Sink Over Ride
        3. 10.2.2.3 HPD Sink Over Ride
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 SN75DP130 Power Sequencing
      1. 11.1.1 Power-Up Sequence:
      2. 11.1.2 Power-Down Sequence:
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Differential Traces
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN75DP130 offers separate AUX and DDC source interfaces that connect to a single AUX sink channel. This minimizes component count when implemented with a graphics processor (GPU) comprising separate DDC and AUX interfaces. For GPUs with combined DDC/AUX, the device can operate as a FET switch to short circuit the AUX channel AC coupling caps while connected to a TMDS sink device.

The configuration shown in Figure 21 supports a GPU with separate DDC and AUX interfaces, and overcomes the need for an external AUX to DDC switch. This circuit provides back current protection into the GPU AUX, HPD, and CAD inputs.

SN75DP130 re2_dvr_conf_llse57.gifFigure 21. DP++ Dual-Mode in a Split AUX/DDC Configuration

The configuration shown in Figure 22 is preferred to avoid very long AUX signal stub lines. Furthermore, this configuration provides isolation between the DP connector and the GPU.

SN75DP130 re3_dvr_conf_llse57.gifFigure 22. DP Only Configuration with AUX Pass Through

The configuration shown in Figure 23 enables the SN75DP130 in DP++ Dual-Mode with the AUX input only monitoring the AUX channel. Use this setting when AUX stub lines can be kept short and minimum AUX attenuation is desired. For DP v1.1a, the stub length shall not exceed 4cm each, and for DP v1.2 with FAUX support each stub line shall be shorter than 1cm.

SN75DP130 re4_dvr_conf_llse57.gifFigure 23. DP++ Dual-Mode Configuration with AUX Monitor

The alternate configuration shown in Figure 24 allows a reduced BOM by eliminating the need for external FET switches while routing AUX and DDC externally, which eliminates any insertion loss cases of AUX is brought through the SN75DP130. For DP v1.2 with FAUX support each stub line shall be shorter than 1cm.

SN75DP130 re5_dvr_conf_llse57.gifFigure 24. Alternate Low-BOM DP++ Dual-Mode Configuration

The previous application examples were specifically concerned with source side implementations of the SN75DP130. Even though source applications (notebook, docking station, and so forth) are the primary target application for the DP130A, the DP130A can also be used in a sink application, such as a DisplayPort monitor. The reader is referred to SLLA349 (Implementation Guide: DP130 in a Sink) for a detailed discussions of the implementation guidelines for sink applications.

10.2 Typical Application

The configuration shown in Figure 25 supports a GPU with unified AUX/DDC interfaces. This circuit provides back current protection into the GPU AUX, HPD, and CAD inputs.

SN75DP130 typicalapp1.pngFigure 25. Typical Application Schematic

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 30 as the input parameters.

Table 30. Design Parameters

DESIGN PARAMETERS VALUE
VCC power supply 3.3 V
VDD power supply 1.1 V
DP single-ended impedance 50 Ω

10.2.2 Detailed Design Procedure

10.2.2.1 Logic I2C Interface

The internal registers of the SN75DP130 are accessed through the SCL_CTL pin and 3 SDA_CTL pin. The 7-bit I2C slave address of the DP130 is determined by the ADDR_EQ pin 4.

Table 31. I2C Slave Address Selection

ADDR_EQ 7-BIT I2C SLAVE ADDRESS READ SLAVE ADDRESS WRITE SLAVE ADDRESS
Low (VIL) 7’b0101100 'h59 'h58
VCC/2 (VIM) 7’b0101101 'h5B 'h5A
High (VIH) 7’b0101110 'h5D 'h5C

10.2.2.2 CAD Sink Over Ride

For testing and debug purposes, leave a place holder on the CAD_SNK input in order to have the option to independently set the DP130 in DP or TMDS mode. A 2k pull-up on this place holder will set the DP130 in TMDS mode independent of the Sink.

10.2.2.3 HPD Sink Over Ride

For testing and debug purposes, leave a place holder on the HPD_SNK input in order to have the option to force the presence of the sink. A 2k pull-up on this place holder will provide an indication of the sink presence.

10.2.3 Application Curves

SN75DP130 eyediagram1.pngFigure 26. Input Into DP130
SN75DP130 eyediagram2.pngFigure 27. Eye Diagram (EQ = 3.5 dB)
SN75DP130 eyediagram3.pngFigure 28. Eye Diagram (EQ = 6 dB)
SN75DP130 eyediagram5.pngFigure 30. Eye Diagram (EQ = 10 dB)
SN75DP130 eyediagram7.pngFigure 32. Eye Diagram (EQ = 15 dB)
SN75DP130 eyediagram4.pngFigure 29. Eye Diagram (EQ = 8 dB)
SN75DP130 eyediagram6.pngFigure 31. Eye Diagram (EQ = 13 dB)
SN75DP130 eyediagram8.pngFigure 33. Eye Diagram (EQ = 18 dB)