9.3.1 Reset Signal

The SN75DP130 RSTN input gives control over the device reset and to place the device into shutdown mode. When RSTN is low, all DPCD registers are reset to their default values, and all Main Link lanes are disabled. When the RSTN input returns to a high logic level, the device comes out of the shutdown mode. To turn on the Main Link, it is necessary to either program the DPCD registers through the local I²C interface or to go through a full sequence of Link Training between DP source and DP sink.

It is critical to reset the digital logic of the SN75DP130 after the V_DDD supply is stable (that is, V_DDD has reached the minimum recommended operating voltage). This is achieved by asserting the RSTN input from low to high. A system may provide a control signal to the RSTN signal that transitions low to high after the V_DDD supply is stable, or implement an external capacitor connected between RSTN and GND, to allow delaying the RSTN signal during power up. The implementations are shown in Figure 15 and Figure 16.

Figure 15. External Capacitor Controlled RSTN

Figure 16. RSTN Input from Active Controller

When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the V_DDD supply where a slower ramp-up results in a larger value external capacitor.

Refer to the latest reference schematic for the SN75DP130 device and/or consider approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor.

When implementing a RSTN input from an active controller, it is recommended to use an open-drain driver if the RSTN input is driven. This protects the RSTN input from damage of an input voltage greater than V_DDD.

9.3.2 Hot Plug Detect and Cable Adapter Detect

The SN75DP130 generates the Hot Plug Detect (HPD_SRC) signal to indicate to the source that a sink has been detected. A low HPD_SNK signal input indicates no sink device is connected. When HPD_SNK is high, the CAD_SNK signal indicates whether a DP sink (CAD_SNK=low) or a TMDS sink (CAD_SNK=high).

A sink device can request a source device interrupt by pulling the HPD_SNK signal low for a duration of 0.5 ms to 1 ms. The interrupt passes through the SN75DP130. If the HPD_SNK signal goes low for longer than 2 ms, the DP source determines that the sink device is disconnected. To conserve power, the SN75DP130 will go into a power saving Standby mode after the HPD signal went low for a duration of t_T(HPD).

In the TMDS mode the AUX training logic is disabled and the Main Link transmits with a fixed output voltage swing of 600mVpp; the pre-emphasis level is set to 0 dB. Output swing and pre-emphasis level are also adjustable by I²C interface. In TMDS mode all four Main Link output lanes are enabled.

Through the local I²C interface it is also possible to force the device to ignore HPD_SNK and CAD_SNK, and control HPD_SRC and CAD_SRC directly.

9.3.3 AUX and DDC Configuration

The SN75DP130 offers an AUX source channel (AUX_SRC), AUX sink channel (AUX_SNK), a selectable DDC interface (SDA_DDC/SCL_DDC) for TMDS mode, and a local I²C control interface (SCL_CTL / SDA_CTL). Upon power-up, the SN75DP130 enables the connection between the AUX_SNK to the appropriate source interface based on CAD_SNK. Table 2 describes the switching logic, including the programmability through the local I²C interface.

The DDC interface incorporates 60-kΩ pull-up resistors on SDA_DDC and SCL_DDC, which are turned on when CAD_SNK is high (TMDS mode) but turned off when CAD_SNK is low (DP mode).

9.3.4 Main Link Configuration

The EQ input stage is self-configuring based on Link Training. A variety of EQ settings are available through external pin configuration to accommodate for different PCB loss and GPU settings, and the I²C interface may be used to fully customize EQ configuration lane-by-lane beyond the input pin configurability options, as described in Table 3.

9.3.5 Link Training and DPCD

The SN75DP130 monitors the auxiliary interface access to DisplayPort Configuration Data (DPCD) registers during Link Training in DP mode to select the output voltage swing V_OD, output pre-emphasis, and the EQ setting of the Main Link. The AUX monitor for SN75DP130 supports Link Training in 1Mbps Manchester mode, and is disabled during TMDS mode (CAD_SNK=VIH).

The AUX channel is further monitored for the DisplayPort D3 standby command.

The DPCD registers monitored by SN75DP130 are listed in Figure 17. Bit fields not listed are reserved and values written to reserved fields are ignored.

9.3.6 Equalization

The SN75DP130 includes a flexible continuous time linear equalizer (CTLE) to compensate for trace or cable loss at its input. When the SN75DP130 is in DP mode, the equalization is self-configuring based on link training commands that are monitored on the AUX channel. The host can configure the desired equalization values, on a lane-by-lane basis, through I²C control. These I²C equalization values are then automatically implemented based on the results of link training.

When the SN75DP130 is in TMDS mode, the equalization applied is based on external pin settings and I²C settings. (See Table 3 for details.)

9.3.7 Configurable Outputs

The SN75DP130 driver on each channel provides flexibility in setting output voltage swing as well as driver de-emphasis. Four levels of output voltage swing and four levels of de-emphasis settings are independently available. Channel equalization coupled with output configurability allows for optimizing the device output eyes across a wide range of channel environments.

9.3.8 Squelch

The SN75DP130 incorporates selectable output signal squelch for conditions when the device input signal does not meet preset thresholds. Main link lane 0 incorporates an activity detector which is enabled through I²C control. The activity detection threshold is selectable, through I²C, from four predefined values ranging from 40 mVpp to 250 mVpp. When squelch is enabled and the activity monitor determines that the lane O input signal falls below the selected threshold, the device output drivers are disabled.

Table 5. Description of SN75DP130 Operating Modes

Table 6. Description of Operating Mode Transitions

9.5.1 I²C Interface Overview

The SN75DP130 I²C interface is enabled when EN and RSTN are input high. The SCL_CTL and SDA_CTL terminals are used for I²C clock and I²C data respectively. The SN75DP130 I²C interface conforms to the two-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the standard mode transfer up to 100 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN75DP130 is factory preset to 01011xx with the two least significant bits being determined by the ADDR_EQ 3-level control input. Figure 19 clarifies the SN75DP130 target address.

The following procedure is followed to write to the SN75DP130 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SN75DP130 7-bit address and a zero-value "W/R" bit to indicate a write cycle
2. The SN75DP130 acknowledges the address cycle
3. The master presents the sub-address (I²C register within SN75DP130) to be written, consisting of one byte of data, MSB-first
4. The SN75DP130 acknowledges the sub-address cycle
5. The master presents the first byte of data to be written to the I²C register
6. The SN75DP130 acknowledges the byte transfer
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN75DP130
8. The master terminates the write operation by generating a stop condition (P)

The following procedure is followed to read the SN75DP130 I²C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the SN75DP130 7-bit address and a one-value "W/R" bit to indicate a read cycle
2. The SN75DP130 acknowledges the address cycle
3. The SN75DP130 transmit the contents of the memory registers MSB-first starting at register 00h.
4. The SN75DP130 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer
5. If an ACK is received, the SN75DP130 transmits the next byte of data
6. The master terminates the read operation by generating a stop condition (P)

No sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I²C master terminates the read operation.

Refer to SN75DP130 Local I2C Control and Status Registers for SN75DP130 local I²C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored.

9.6.1 SN75DP130 Local I²C Control and Status Registers