Product details

Protocols DisplayPort Speed (Max) (Gbps) 5.4 Supply voltage (V) 3.3 Operating temperature range (C) 0 to 85
Protocols DisplayPort Speed (Max) (Gbps) 5.4 Supply voltage (V) 3.3 Operating temperature range (C) 0 to 85
VQFN (RGZ) 48 49 mm² 7 x 7
  • Supports DP v1.1a and DP v1.2 Signaling
    Including HBR2 Data Rates to 5.4 Gbps
  • Supports HDMI 1.4a With TMDS Clock
    Frequencies up to 340 MHz
  • Glueless Interface to AMD, Intel, and NVIDIA
    Graphics Processors
  • Auto-Configuration Through Link Training
  • Output Signal Conditioning With Tunable Voltage
    Swing and Pre-Emphasis Gain
  • Highly Configurable Input Variable Equalizer
  • Two Device Options Including a Dual Power
    Supply Configuration for Lowest Power
  • 2-kV ESD HBM Protection
  • Temperature Range: 0°C to 85°C
  • 48-Pin 7-mm × 7-mm VQFNPackage
  • Supports DP v1.1a and DP v1.2 Signaling
    Including HBR2 Data Rates to 5.4 Gbps
  • Supports HDMI 1.4a With TMDS Clock
    Frequencies up to 340 MHz
  • Glueless Interface to AMD, Intel, and NVIDIA
    Graphics Processors
  • Auto-Configuration Through Link Training
  • Output Signal Conditioning With Tunable Voltage
    Swing and Pre-Emphasis Gain
  • Highly Configurable Input Variable Equalizer
  • Two Device Options Including a Dual Power
    Supply Configuration for Lowest Power
  • 2-kV ESD HBM Protection
  • Temperature Range: 0°C to 85°C
  • 48-Pin 7-mm × 7-mm VQFNPackage

The SN75DP130 device is a single channel DisplayPort™ (DP) re-driver that regenerates the DP high-speed digital link. The device complies with the VESA DisplayPort Standard Version 1.2, and supports a 4-lane Main Link interface signaling up to HBR2 rates at 5.4 Gbps per lane. This device also supports DP++ Dual-Mode, offering TMDS signaling for DVI and full HDMI Version 1.4a support.

The device compensates for PCB-related frequency loss and switching-related loss to provide the optimum DP electrical performance from source to sink. The Main Link signal inputs feature configurable equalizers with selectable boost settings. At the Main Link output, four primary levels of differential output voltage swing (VOD) and four primary levels of pre-emphasis are available. A secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust the output signaling levels and input equalizers in response to Link Training commands. Additionally, the SN75DP130 output signal conditioning and EQ parameters are fully programmable through the I2C interface.

The SN75DP130 is optimized for mobile applications, and contains activity detection circuitry on the Main Link input that transitions to a low-power Output Disable mode in the absence of a valid input signal. Other low-power modes are supported, including a standby mode with typical dissipation of approximately 2 mW when no video sink (for example, monitor) is connected.

The device is characterized for an extended operational temperature range from 0°C to 85°C.

The SN75DP130 offers separate AUX and DDC source interfaces that connect to one AUX sink channel. This minimizes component count when implemented with a graphics processor (GPU) comprising separate DDC and AUX interfaces. For GPUs with combined DDC/AUX, the device can operate as a FET switch to short-circuit the AUX channel AC coupling caps while connected to a TMDS sink device. Other sideband circuits such as Hot Plug Detect (HPD) are optimized to reduce external components, providing a seamless connection to Intel, AMD, and NVIDIA graphics processors.

The SN75DP130 device is a single channel DisplayPort™ (DP) re-driver that regenerates the DP high-speed digital link. The device complies with the VESA DisplayPort Standard Version 1.2, and supports a 4-lane Main Link interface signaling up to HBR2 rates at 5.4 Gbps per lane. This device also supports DP++ Dual-Mode, offering TMDS signaling for DVI and full HDMI Version 1.4a support.

The device compensates for PCB-related frequency loss and switching-related loss to provide the optimum DP electrical performance from source to sink. The Main Link signal inputs feature configurable equalizers with selectable boost settings. At the Main Link output, four primary levels of differential output voltage swing (VOD) and four primary levels of pre-emphasis are available. A secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust the output signaling levels and input equalizers in response to Link Training commands. Additionally, the SN75DP130 output signal conditioning and EQ parameters are fully programmable through the I2C interface.

The SN75DP130 is optimized for mobile applications, and contains activity detection circuitry on the Main Link input that transitions to a low-power Output Disable mode in the absence of a valid input signal. Other low-power modes are supported, including a standby mode with typical dissipation of approximately 2 mW when no video sink (for example, monitor) is connected.

The device is characterized for an extended operational temperature range from 0°C to 85°C.

The SN75DP130 offers separate AUX and DDC source interfaces that connect to one AUX sink channel. This minimizes component count when implemented with a graphics processor (GPU) comprising separate DDC and AUX interfaces. For GPUs with combined DDC/AUX, the device can operate as a FET switch to short-circuit the AUX channel AC coupling caps while connected to a TMDS sink device. Other sideband circuits such as Hot Plug Detect (HPD) are optimized to reduce external components, providing a seamless connection to Intel, AMD, and NVIDIA graphics processors.

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Technical documentation

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Type Title Date
* Data sheet SN75DP130 DisplayPort™ 1:1 Redriver With Link Training datasheet (Rev. E) 31 Mar 2015
Application note High-Speed Layout Guidelines for Signal Conditioners and USB Hubs 14 Jun 2018
Technical article How to select a redriver or retimer for HDMI 2.0 jitter cleansing 01 May 2017
White paper Build a true fidelity system using video signal conditioners 09 Jun 2016
Application note Implementation Guide: DP130 in a Sink 13 Sep 2014
User guide SN75DP130 EVM Users Manual (Rev. A) 20 Jan 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DP130DSEVM — DP130 Dual-Source Evaluation Module

The SN75DP130DSEVM is designed to provide easy evaluation of the SN75DP130DS device. It is also meant to serve as a reference design to show a practical example of how to use the device in a mass-production system. The SN75DP130DS is a high-speed one-to-one redriver for Display Port signals with a (...)
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Evaluation board

DP130SSEVM — DP130 Single-Source Evaluation Module

The SN75DP130SSEVM is designed to provide easy evaluation of the SN75DP130SS device. It is also meant to serve as a reference design to show a practical example of how to use the device in a mass-production system. The SN75DP130SS is a high-speed one-to-one redriver for Display Port signals with a (...)
In stock
Limit: 1
Simulation model

SN75DP130 HSpice Linux Model

SLLM137.ZIP (600 KB) - HSpice Model
Simulation model

SN75DP130 HSpice Windows Model

SLLM138.ZIP (382 KB) - HSpice Model
Simulation model

DP130 IBIS-AMI Model

SLLM318.ZIP (1638 KB) - IBIS-AMI Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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VQFN (RGZ) 48 View options

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