SLASEC2B November 2016 – February 2019 TAS2557
Audio data is transferred between the host processor and the TAS2557 via the digital audio serial interface (ASI), or audio bus. The ASI buses (ASI1 and ASI2) can be configured for left or right-justified, I2S, DSP, or TDM modes of operation. Standard telephony PCM interfaces are supported within the TDM mode.. These modes are all MSB-first, with data width programmable to 16, 20, 24, or 32 bits. In addition, the WCLK and BCLK can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.
|ASI1_FORMAT[4:2] (ASI1_MODE)||ASI2_FORMAT[4:2] (ASI2_MODE)||ASI Function Mode|
|000||000||I2S Mode (default)|
|010||010||Right-Justified Mode (RJF)|
|011||011||Left-Justified Mode (LJF)|
|100||100||Mono PCM Mode|
|ASI1_FORMAT[1:0] (ASI1_LENGTH)||ASI2_FORMAT[1:0] (ASI2_LENGTH)||Word Length|
|10||10||24 bits (default)|
The bit clock (BCLK) is used to clock in and clock out the digital audio data across the serial bus. This signal can be programmed to generate variable clock pulses by controlling the BCLK multiply-divide factor in Registers 0x08 through 0x10. The number of BCLK pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TAS2557 devices may share the same audio bus.
The TAS2557 also includes a feature to offset the position of start of data transfer with respect to the wordclock (WCLK). This offset is specified in number of BCLKs. This can be used in cases where there is a non-zero bit-clock delay from WCLK edge or to support TDM modes of operation. The TAS2557 can place the DOUT line into a Hi-Z (tri-state) condition during all BCLKs when valid data is not being sent. TDM mode is useable with I2S, LJF, RJF, and DSP interface modes and is required for stereo applications when more than one TAS2557 part is used. The TAS2557 also has a bus keeper circuit that can be enabled in tri-sate mode. The bus-keeper is a weak internal latch that will hold the data line state without the need for external pull-up or pull-down resistors while signal lines are in the Hi-Z or non-driven state.
|ASI1_OFFSET_1 (ASI_OFFSET1)||ASI2_OFFSET_1 (ASI2_OFFSET1)||BCLKs from WCLK edge for data channel|
|ASI1_FORMAT (ASI1_TRISTATE)||ASI2_FORMAT (ASI2_TRISTATE)||Tri-state DOUT for extra BCLK cycles after frame is complete|
|ASI1_BUSKEEP (ASI1_BKP)||ASI2_BUSKEEP (ASI2_BKP)||Tri-state DOUT for extra BCLK cycles after frame is complete|
Additional configuration options for the ASI1 and ASI2 interface can be found in the Register Map. It is recommended to use the PurePath Console 3 Software TAS2557 Application software for TAS2557 to configure the ASI interfaces.