SLASEC2B November 2016 – February 2019 TAS2557
The TAS2557 operates as an I2C slave over the IOVDD voltage range. It is adjustable to one of four I2C addresses. This allows multiple TAS2557 devices in a system to connect to the same I2C bus. The I2C pins are fail-safe. If the part is not powered or is in shutdown the I2C pins will not impact the I2C bus allowing it to remain functional.
To configure the TAS2557 for I2C operation set the SPI_SELECT pin to ground. The I2C address can then be set using pins ADR0_SCLK and ADR1_MSIO according to Table 1. The pins configure the two LSB bits of the following 7-bit binary address A6-A0 of 10011xx. This permits the I2C address of TAS2557 to be 0x4C(7-bit) through 0x4F(7-bit). For example, if both ADR0_SCLK and ADR1_MSIO are connected to ground the I2C address for the TAS2557 would be 0x4C(7-bit). This is equivalent to 0x98 (8-bit) for writing and 0x99 (8-bit) for reading.
|ADR0_SCLK Pin Connection||ADR1_MSIO Pin Connection||I2C Device Address|
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The corresponding pins on the TAS2557 for the two signals are SDA_MOSI and SCL_SSZ. The bus transfers data serially, one bit at a time. The address and data (8-bit) bytes are transferred most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 19 shows a typical sequence.
The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection.
Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up resistors between 660 Ω and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the device supply voltage, IOVDD.
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 19 shows a generic data transfer sequence.