SLASEG8A March 2016 – July 2017 TAS5782M
The TAS5782M device integrates 4 main building blocks together into a single cohesive device that maximizes sound quality, flexibility, and ease of use. The 4 main building blocks are listed below:
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low-voltage digital and analog circuitry. Another supply, called PVDD, is required to provide power to the output stage of the audio amplifier. The operating range for these supplies is shown in the Recommended Operating Conditions table.
Communication with the device is accomplished through the I2C control port. A speaker amplifier fault line is also provided to notify a system controller of the occurrence of an overtemperature , overcurrent, or DC error in the speaker amplifier. Two digital GPIO pins are available for use. In the selectable process flows of the TAS5782M, the GPIO2 pin is used as an SDOUT terminal. The other GPIO is unused.
The µCDSP audio processing core is pre-programmed with a configurable DSP program. The PPC3 provides a means by which to manipulate the controls associated with that Process Flow.
The TAS5782M device has a power-on reset function. The power-on reset feature resets all of the registers to their default configuration as the device is powering up. When the low-voltage power supply used to power DVDD, AVDD, and CPVDD exceeds the POR threshold, the device sets all of the internal registers to their default values and holds them there until the device receives valid MCLK, SCLK, and LRCK/FS toggling for a period of approximately 4 ms. After the toggling period has passed, the internal reset of the registers is removed and the registers can be programmed via the I2C Control Port.
The TAS5782M devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio Interface in one form or another.
Figure 64 shows the basic data flow at basic sample rate (fS). When the data is brought into the serial audio interface, the data is processed, interpolated and modulated to 128 × fS before arriving at the current segments for the final digital to analog conversion.
Figure 65 shows the clock tree.
The Serial Audio Interface typically has 4 connection pins which are listed as follows:
The device has an internal PLL that is used to take either MCLK or SCLK and create the higher rate clocks required by the DSP and the DAC clock.
In situations where the highest audio performance is required, bringing MCLK to the device along with SCLK and LRCK/FS is recommended. The device should be configured so that the PLL is only providing a clock source to the DSP. All other clocks are then a division of the incoming MCLK. To enable the MCLK as the main source clock, with all others being created as divisions of the incoming MCLK, set the DAC CLK source Mux (SDAC in Figure 65) to use MCLK as a source, rather than the output of the MCLK/PLL Mux.
In Master Mode, the device generates bit clock and left-right and frame sync clock and outputs them on the appropriate pins. To configure the device in master mode, first put the device into reset, then use registers SCLKO and LRKO (P0-R9). Then reset the LRCK/FS and SCLK divider counters using bits RSCLK and RLRK (P0-R12). Finally, exit reset.
Figure 66 shows a simplified serial port clock tree for the device in master mode.
In master mode, MCLK is an input and SCLK and LRCK/FS are outputs. SCLK and LRCK/FS are integer divisions of MCLK. Master mode with a non-audio rate master clock source requires external GPIO’s to use the PLL in standalone mode. The PLL should be configured to ensure that the on-chip processor can be driven at the maximum clock rate. The master mode of operation is described in the Clock Master from a Non-Audio Rate Master Clock section.
When used with audio rate master clocks, the register changes that should be done include switching the device into master mode, and setting the divider ratio. An example of the master mode of operations is using 24.576 MHz MCLK as a master clock source and driving the SCLK and LRCK/FS with integer dividers to create 48 kHz sample rate clock output. In master mode, the DAC section of the device is also running from the PLL output. The TAS5782M device is able to meet the specified audio performance while using the internal PLL. However, using the MCLK CMOS oscillator source will have less jitter than the PLL.
To switch the DAC clocks (SDAC in the Figure 65) the following registers should be modified
The classic example here is running a 96-kHz sampling system. Given the clock tree for the device (shown in Figure 65), a non-audio clock rate cannot be brought into the MCLK to the PLL in master mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.
The clock flow through the system is shown in Figure 67. The newly generated MCLK must be brought out of the device on a GPIO pin, then brought into the MCLK pin for integer division to create SCLK and LRCK/FS outputs.
Pull-up resistors should be used on SCLK and LRCK/FS in master mode to ensure the device remains out of sleep mode.
The TAS5782M device requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the MCLK input and supports up to 50 MHz. The TAS5782M device system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 32 kHz, (44.1 – 48 kHz), (88.2 – 96 kHz) are supported.
Values in the parentheses are grouped when detected, for example, 88.2 kHz and 96 kHz are detected as double rate, 32 kHz, 44.1 kHz and 48 kHz are detected as single rate and so on.
Also note, there is one process flow which has only a (1/2)X SRC.
In the presence of a valid bit MCLK, SCLK and LRCK/FS, the device automatically configures the clock tree and PLL to drive the µCDSP as required.
The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common audio sampling rates.
MCLK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are supported by configuring various PLL and clock-divider registers directly. In slave mode, auto clock mode should be disabled using P0-R37. Additionally, the user can be required to ignore clock error detection if external clocks are not available for some time during configuration or if the clocks presented on the pins of the device are invalid. The extended programmability allows the device to operate in an advanced mode in which the device becomes a clock master and drive the host serial port with LRCK/FS and SCLK, from a non-audio related clock (for example, using a setting of 12 MHz to generate 44.1 kHz [LRCK/FS] and 2.8224 MHz [SCLK]).
Table 2 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise. For MCLK timing requirements, refer to the Serial Audio Port Timing – Master Mode section.
|SYSTEM CLOCK FREQUENCY (fMCLK) (MHz)|
|64 fS||128 fS||192 fS||256 fS||384 fS||512 fS|
The TAS5782M device supports a wide range of options to generate the required clocks as shown in Figure 65.
The clocks for the PLL require a source reference clock. This clock is sourced as the incoming SCLK or MCLK, a GPIO can also be used.
The source reference clock for the PLL reference clock is selected by programming the SRCREF value on P0-R13, D[6:4]. The TAS5782M device provides several programmable clock dividers to achieve a variety of sampling rates. See Figure 65.
If PLL functionality is not required, set the PLLEN value on P0-R4, D to 0. In this situation, an external master clock is required.
|DSCLK||External SCLK Div||B0-P0-R32-D[6:0]|
|DLRK||External LRCK/FS Div||B0-P0-R33-D[7:0]|
The TAS5782M device has an on-chip PLL with fractional multiplication to generate the clock frequency required by the Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.
The PLL is enabled by default. The PLL can be enabled by writing to P0-R4, D. When the PLL is enabled, the PLL output clock PLLCK is given by Equation 1:
R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).
When the PLL is enabled and D = 0000, the following conditions must be satisfied:
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:
When the PLL is enabled,
Example: MCLK = 12 MHz and fS = 44.1 kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Values are written to the registers in Table 4.
|PLLE||PLL enable||P0-R4, D|
|PPDV||PLL P||P0-R20, D[3:0]|
|PJDV||PLL J||P0-R21, D[5:0]|
|PDDV||PLL D||P0-R22, D[5:0]|
|PRDV||PLL R||P0-R24, D[3:0]|
|fS (kHz)||Sampling frequency|
|RMCLK||Ratio between sampling frequency and MCLK frequency (MCLK frequency = RMCLK x sampling frequency)|
|MCLK (MHz)||System master clock frequency at MCLK input (pin 20)|
|PLL VCO (MHz)||PLL VCO frequency as PLLCK in Figure 65|
|P||One of the PLL coefficients in Equation 1|
|PLL REF (MHz)||Internal reference clock frequency which is produced by MCLK / P|
|M = K × R||The final PLL multiplication factor computed from K and R as described in Equation 1|
|K = J.D||One of the PLL coefficients in Equation 1|
|R||One of the PLL coefficients in Equation 1|
|PLL fS||Ratio between fS and PLL VCO frequency (PLL VCO / fS)|
|DSP fS||Ratio between operating clock rate and fS (PLL fS / NMAC)|
|NMAC||The clock divider value in Table 3|
|DSP CLK (MHz)||The operating frequency as DSPCK in Figure 65|
|MOD fS||Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)|
|MOD f (kHz)||DAC operating frequency as DACCK in|
|NDAC||DAC clock divider value in Table 3|
|DOSR||OSR clock divider value in Table 3 for generating OSRCK in Figure 65. DOSR must be chosen so that MOD fS / DOSR = 16 for correct operation.|
|NCP||NCP (negative charge pump) clock divider value in Table 3|
|CP f||Negative charge pump clock frequency (fS × MOD fS / NCP)|
|% Error||Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL. Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.
|M = K×R||K = J×D||R||PLL fS||DSP fS||NMAC||DSP CLK
|MOD fS||MOD f
|NDAC||DOSR||% ERROR||NCP||CP f
The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN (pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio interface. Serial data is clocked into the TAS5782M device on the rising edge of SCLK. The LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
|FORMAT||DATA BITS||MAXIMUM LRCK/FS FREQUENCY (kHz)||MCLK RATE (fS)||SCLK RATE (fS)|
|I2S/LJ/RJ||32, 24, 20, 16||Up to 96||128 to 3072 (≤ 50 MHz)||64, 48, 32|
|TDM||32, 24, 20, 16||Up to 48||128 to 3072||125, 256|
|96||128 to 512||125, 256|
The TAS5782M device requires the synchronization of LRCK/FS and system clock, but does not require a specific phase relation between LRCK/FS and system clock.
If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and system clock is completed.
If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and SCLK is completed.
The TAS5782M device supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 68 through Figure 73.
The TAS5782M device also supports right-justified, and TDM data. I2S, LJ, RJ, and TDM are selected using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I2S and 24 bit word length. The I2S slave timing is shown in Figure 20.
shows a detailed timing diagram for the serial audio interface.
In addition to acting as a I2S slave, the TAS5782M device can act as an I2S master, by generating SCLK and LRCK/FS as outputs from the MCLK input. Table 8 lists the registers used to place the device into Master or Slave mode. Please refer to the Serial Audio Port Timing – Master Mode section for serial audio Interface timing requirements in Master Mode. For Slave Mode timing, please refer to the Serial Audio Port Timing – Slave Mode section.
|P0-R9-B0, B4, and B5||I2S Master mode select|
|P0-R32-D[6:0]||SCLK divider and LRCK/FS divider|
The following data formats are only available in software mode.
The TAS5782M device has a zero-detect function. The zero-detect function can be applied to both channels of data as an AND function or an OR function, via controls provided in the control port in P0-R65-D[2:1].Continuous Zero data cycles are counted by LRCK/FS, and the threshold of decision for analog mute can be set by P0-R59, D[6:4] for the data which is clocked in on the left frame of an I2S signal or Slot 1 of a TDM signal and P0-R59, D[2:0] for the data which is clocked in on the right frame of an I2S signal or Slot 2 of a TDM signal as shown in Table 10. Default values are 0 for both channels.
|Bit : 2||0||Zero data triggers for the two channels for zero detection are ORed together.|
|1 (Default)||Zero data triggers for the two channels for zero detection are ANDed together.|
|Bit : 1||0||Zero detection and analog mute are disabled for the data clocked in on the right frame of an I2S signal or Slot 2 of a TDM signal.|
|1 (Default)||Zero detection analog mute are enabled for the data clocked in on the right frame of an I2S signal or Slot 2 of a TDM signal.|
|Bit : 0||0||Zero detection analog mute are disabled for the data clocked in on the left frame of an I2S signal or Slot 1 of a TDM signal.|
|1 (Default)||Zero detection analog mute are enabled for the data clocked in on the left frame of an I2S signal or Slot 1 of a TDM signal.|
|ATMUTETIML OR ATMA||NUMBER OF LRCK/FS CYCLES||TIME at 48 kHz|
|0 0 0||1024||21 ms|
|0 0 1||5120||106 ms|
|0 1 0||10240||213 ms|
|0 1 1||25600||533 ms|
|1 0 0||51200||1.066 secs|
|1 0 1||102400||2.133 secs|
|1 1 0||256000||5.333 secs|
|1 1 1||512000||10.66 secs|
To play audio after the device is powered up or reset the device must be enabled by writing book 0x00, page 0x00, register 0x02 to 0x00.
The following is a sample script for enabling the device:
#Enable DUT w 90 00 00 #Go to page 0 w 90 7f 00 #Go to book 0 w 90 02 00 #Enable device
For more information regarding the TAS5782 flexible processing system, see the TAS5782M Process Flows
Ramp-up frequency and ramp-down frequency can be controlled by P0-R63, D[7:6] and D[3:2] as shown in Table 11. Also ramp-up step and ramp-down step can be controlled by P0-R63, D[5:4] and D[1:0] as shown in Table 12.
|RAMP UP SPEED||EVERY N fS||COMMENTS||RAMP DOWN FREQUENCY||EVERY N fS||COMMENTS|
|11||Direct change||11||Direct change|
|RAMP UP STEP||STEP dB||COMMENTS||RAMP DOWN STEP||STEP dB||COMMENTS|
Emergency ramp down of the volume is provided for situations such as I2S clock error and power supply failure. Ramp-down speed is controlled by P0-R64-D[7:6]. Ramp-down step can be controlled by P0-R64-D[5:4]. Default is ramp-down by every fS cycle with –4dB step.
The voltage divider between the GVDD_REG pin and the SPK_GAIN/FREQ pin is used to set the gain and switching frequency of the amplifier. Upon start-up of the device, the voltage presented on the SPK_GAIN/FREQ pin is digitized and then decoded into a 3-bit word which is interpreted inside the TAS5782M device to correspond to a given gain and switching frequency. In order to change the SPK_GAIN or switching frequency of the amplifier, the PVDD must be cycled off and on while the new voltage level is present on the SPK_GAIN/FREQ pin.
Because the amplifier adds gain to both the signal and the noise present in the audio signal, the lowest gain setting that can meet voltage-limited output power targets should be used. Using the lowest gain setting ensures that the power target can be reached while minimizing the idle channel noise of the system. The switching frequency selection affects three important operating characteristics of the device. The three affected characteristics are the power dissipation in the device, the power dissipation in the inductor, and the target output filter for the application.
Higher switching frequencies typically result in slightly higher power dissipation in the TAS5782M device and lower dissipation in the inductor in the system, due to decreased ripple current through the inductor and increased charging and discharging current in device and parasitic capacitances. Switching at the higher of the available switching frequencies will result in lower overall dissipation in the system and lower operating temperature of the inductors. However, the thermally limited power output of the device can be decreased in this situation, because some of the TAS5782M device thermal headroom will be absorbed by the higher switching frequency. Conversely inductor heating can be reduced by using the higher switching frequency to reduce the ripple current.
Another advantage of increasing the switching frequency is that the higher frequency carrier signal can be filtered by an L-C filter with a higher corner frequency, leading to physically smaller components. Use the highest switching frequency that continues to meet the thermally limited power targets for the application. If thermal constraints require heat reduction in the TAS5782M device, use a lower switching rate.
The switching frequency of the speaker amplifier is dependent on an internal synchronizing signal, (fSYNC), which is synchronous with the sample rate. The rate of the synchronizing signal is also dependent on the sample rate. Refer to Table 13 below for details regarding how the sample rates correlate to the synchronizing signal.
Table 14 summarizes the de-code of the voltage presented to the SPK_GAIN/FREQ pin. The voltage presented to the SPK_GAIN/FREQ pin is latched in upon startup of the device. Subsequent changes require power cycling the device. A gain setting of 20 dB is recommended for nominal supply voltages of 13 V and lower, while a gain of 26 dB is recommended for supply voltages up to 26.4 V. Table 14 shows the voltage required at the SPK_GAIN/FREQ pin for various gain and switching scenarios as well some example resistor values for meeting the voltage range requirements.
|VSPK_GAIN/FREQ (V)||RESISTOR EXAMPLES||GAIN MODE||AMPLIFIER SWITCHING FREQUENCY MODE|
|MIN||MAX||R100 (kΩ): RESISTOR TO GROUND
R101 (kΩ): RESISTOR TO GVDD_REG
|5.44||6.6||R100 = 750
R101 = 150
|26 dBV||8 × fSYNC|
|4.67||5.43||R100 = 390
R101 = 150
|6 × fSYNC|
|3.89||4.66||R100 = 220
R101 = 150
|5 × fSYNC|
|3.11||3.88||R100 = 150
R101 = 150
|4 × fSYNC|
|2.33||3.1||R100 = 100
R101 = 150
|20 dBV||8 × fSYNC|
|1.56||2.32||R100 = 56
R101 = 150
|6 × fSYNC|
|0.78||1.55||R100 = 33
R101 = 150
|5 × fSYNC|
|0||0.77||R100 = 8.2
R101 = 150
|4 × fSYNC|
The TAS5782M device continuously monitors die temperature to ensure the temperature does not exceed the OTETHRES level specified in the Recommended Operating Conditions table. If an OTE event occurs, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This is a non-latched error and the device will attempt to self clear after OTECLRTIME has passed.
The TAS5782M device continuously monitors the output current of each amplifier output to ensure the output current does not exceed the OCETHRES level specified in the Recommended Operating Conditions table. If an OCE event occurs, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This is a non-latched error and the device will attempt to self clear after OCECLRTIME has passed.
If the TAS5782M device measures a DC offset in the output voltage, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This latched error requires the SPK_MUTE line to toggle to reset the error. Alternatively, pulling the MCLK, SCLK, or LRCK low causes a clock error, which also resets the device. Normal operation resumes by re-starting the stopped lock.
The TAS5782M device internally monitors the AVDD net to protect against the AVDD supply dropping unexpectedly. To enable this feature, P1-R5-B0 is used.
If the voltage presented on the PVDD supply drops below the UVETHRES(PVDD) value listed in the Recommended Operating Conditions table, the SPK_OUTxx outputs transition to high impedance. This is a self-clearing error, which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions table, the device resumes normal operation.
If the voltage presented on the PVDD supply exceeds the OVETHRES(PVDD) value listed in the Recommended Operating Conditions table, the SPK_OUTxx outputs will transition to high impedance. This is a self-clearing error, which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions table, the device will resume normal operation.
The voltage presented on the PVDD supply only protects up to the level described in the Recommended Operating Conditions table for the PVDD voltage. Exceeding the absolute maximum rating may cause damage and possible device failure, because the levels exceed that which can be protected by the OVE protection circuit.
The SPK_MUTE pin can also be used to monitor a system voltage, such as a LCD TV backlight, a battery pack in portable device, by using a voltage divider created with two resistors (see Figure 74).
Figure 75 shows a timing diagram for external undervoltage error protection.
The SPK_MUTE input pin voltage range is provided in the Recommended Operating Conditions table. The ratio of external resistors must produce a voltage within the provided input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the SPK_MUTE pin higher than the level specified in the Recommended Operating Conditions table, potentially causing damage to or failure of the device. Therefore, any monitored voltage (including all ripple, power supply variation, resistor divider variation, transient spikes, and others) must be scaled by the resistor divider network to never drive the voltage on the SPK_MUTE pin higher than the maximum level specified in the Recommended Operating Conditions table.
When the divider is set correctly, any DC voltage can be monitored. Figure 74 shows a 12-V example of how the SPK_MUTE is used for external undervoltage error protection.
When a clock error is detected on the incoming data clock, the TAS5782M device switches to an internal oscillator and continues to the drive the DAC, while attenuating the data from the last known value. Once this process is complete, the DAC outputs will be hard muted to the ground and the class D PWM output will stop switching. The clock error can be monitored at B0-P0-R94 and R95. The clock error status bits are non-latching, except for MCLK halted B0-P0-R95-D and CERF B0-P0-R95-D which are cleared when read.
The TAS5782M device supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave device. Because the TAS5782M register map spans several books and pages, the user must select the correct book and page before writing individual register bits or bytes. Changing from book to book is accomplished by first changing to page 0x00 by writing 0x00 to register 0x00 and then writing the book number to register 0x7f of page 0. Changing from page to page is accomplished via register 0x00 on each page. The register value selects the register page, from 0 to 255.
The TAS5782M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are factory preset to 10010 (0x9x). The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus at one time, which gives a range of 0x90, 0x92, 0x94 and 0x96, as detailed in Table 16. Each TAS5782M device responds when it receives the slave address.
|ADR1||ADR0||I2C SLAVE ADDRESS [R/W]|
Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations. The TAS5782M device supports auto-increment mode automatically. Auto-increment stops at page boundaries.
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The TAS5782M device supports only slave receivers and slave transmitters.
|Data Type||St||slave address||R/||ACK||DATA||ACK||DATA||ACK||ACK||Sp|
|Data Type||St||slave address||R/||ACK||DATA||ACK||DATA||ACK||NACK||Sp|
M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition
A master can write to any TAS5782M device registers using single or multiple accesses. The master sends a TAS5782M device slave address with a write bit, a register address, and the data. If auto-increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the data is received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 19 shows the write operation.
|Data Type||St||slave addr||W||ACK||inc||reg addr||ACK||write data 1||ACK||write data 2||ACK||ACK||Sp|
M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge
A master can read the TAS5782M device register. The value of the register address is stored in an indirect index register in advance. The master sends a TAS5782M device slave address with a read bit after storing the register address. Then the TAS5782M device transfers the data which the index register points to. When auto-increment is enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 20 lists the read operation.
|Data Type||St||slave addr||W||ACK||inc||reg addr||ACK||Sr||slave addr||R||ACK||data||ACK||NACK||Sp|
M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition; W = Write; R = Read; NACK = Not acknowledge
To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book. On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book number to register 0x7f on page 0. To change between pages in a book, simply write the page number to register 0x00.
The swap flag is used to copy the audio coefficient from the host memory to the DSP memory. The swap flag feature is important to maintain the stability of the BQs. A BQ is a closed-loop system with 5 coefficients. To avoid instability in the BQ in an update transition between two different filters, update all five parameters within one audio sample. The internal swap flag insures all 5 coefficients for each filter are transferred from host memory to DSP memory occurs within an audio sample. The swap flag stays high until the full host buffer is transferred to DSP memory. Updates to the Host buffer should not be made while the swap flag is high.
All writes to book 0x8C from page 0x11 and register 0x58 through page 0x21 and register 0x78 require the swap flag. The swap flag is located in book 0x8C, page 0x23, and register 0x14 and must be set to 0x00 00 00 01 for a swap.
w 90 00 00 #Go to page 0 w 90 7f 8c #Change the book to 0x8C w 90 00 1e #Go to page 0x1E w 90 44 00 80 00 00 #Fine volume Left w 90 48 00 80 00 00 #Fine volume Right #Run the swap flag for the DSP to work on the new coefficients w 90 00 00 #Go to page 0 w 90 7f 8c #Change the book to 0x8C w 90 00 23 #Go to page 0x23 w 90 14 00 00 00 01 #Swap flag
Because the TAS5782M device is a highly configurable device, numerous modes of operation can exist for the device. For the sake of succinct documentation, these modes are divided into two modes:
Fundamental operating modes are the primary modes of operation that affect the major operational characteristics of the device, which are the most basic configurations that are chosen to ensure compatibility with the intended application or the other components that interact with the device in the final system. Some examples of the operating modes are the communication protocol used by the control port, the output configuration of the amplifier, or the Master/Slave clocking configuration.
The fundamental operating modes are described starting in the Serial Audio Port Operating Modes section.
Secondary usage modes are best described as modes of operation that are used after the fundamental operating modes are chosen to fine tune how the device operates within a given system. These secondary usage modes can include selecting between left justified and right justified Serial Audio Port data formats, or enabling some slight gain/attenuation within the DAC path. Secondary usage modes are accomplished through manipulation of the registers and controls in the I2C control port. Those modes of operation are described in their respective register/bit descriptions and, to avoid redundancy, are not included in this section.
The serial audio port in the TAS5782M device supports industry-standard audio data formats, including I2S, Time Division Multiplexing (TDM), Left-Justified (LJ), and Right-Justified (RJ) formats. To select the data format that will be used with the device, controls are provided on P0-R40. The timing diagrams for the serial audio port are shown in the Serial Audio Port Timing – Slave Mode section, and the data formats are shown in the Serial Audio Port – Data Formats and Bit Depths section.
The TAS5782M device is configured via an I2C communication port. The device does not support a hardware only mode of operation, nor Serial Peripheral Interface (SPI) communication. The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements are described in the I2C Bus Timing – Standard and I2C Bus Timing – Fast sections.
The TAS5782M device can be used in two different amplifier configurations:
The familiar stereo mode of operation uses the TAS5782M device to amplify two independent signals, which represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented on differential output pairs shown as SPK_OUTA± and SPK_OUTB±. The routing of the audio data which is presented on the SPK_OUTxx outputs can be changed according to the Audio Process Flow which is used and the configuration of registers P0-R42-D[5:4] and P0-R42-D[1:0]. The familiar stereo mode of operation is shown in .
By default, the TAS5782M device is configured to output the Right frame of a I2S input on the Channel A output and the left frame on the Channel B output.
The mono mode of operation is used to describe operation in which the two outputs of the device are placed in parallel with one another to increase the power sourcing capabilities of the audio output channel. This is also known as Parallel Bridge Tied Load (PBTL).
On the output side of the TAS5782M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter PBTL. However, the two outputs may be required to merge together after the inductor portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive inductors to be used because the current is divided between the two inductors. This process is called Post-Filter PBTL. Both variants of mono operation are shown in Figure 78 and Figure 79.
On the input side of the TAS5782M device, the input signal to the mono amplifier can be selected from the any slot in a TDM stream or the left or right frame from an I2S, LJ, or RJ signal. The TAS5782M device can also be configured to amplify some mixture of two signals, as in the case of a subwoofer channel which mixes the left and right channel together and sends the mixture through a low-pass filter to create a mono, low-frequency signal.
The mono mode of operation is shown in the Mono (PBTL) Systems section.
The digital audio serial port in the TAS5782M device can be configured to receive clocks from another device as a serial audio slave device. The slave mode of operation is described in the Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM) section. If no system processor is available to provide the audio clocks, the TAS5782M device can be placed into Master Mode. In master mode, the TAS5782M device provides the clocks to the other audio devices in the system. For more details regarding the Master and Slave mode operation within the TAS5782M device, see the Serial Audio Port Operating Modes section.