SLASEG8A March   2016  – July 2017 TAS5782M


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 Internal Pin Configurations
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation Characteristics
    7. 7.7  MCLK Timing
    8. 7.8  Serial Audio Port Timing - Slave Mode
    9. 7.9  Serial Audio Port Timing - Master Mode
    10. 7.10 I2C Bus Timing - Standard
    11. 7.11 I2C Bus Timing - Fast
    12. 7.12 SPK_MUTE Timing
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. Parametric Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-on-Reset (POR) Function
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port
        1. Clock Master Mode from Audio Rate Master Clock
        2. Clock Master from a Non-Audio Rate Master Clock
        3. Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)
          1. Clock Generation using the PLL
          2. PLL Calculation
            1. Examples:
        5. Serial Audio Port - Data Formats and Bit Depths
          1. Data Formats and Master/Slave Modes of Operation
        6. Input Signal Sensing (Power-Save Mode)
      4. 9.3.4 Enable Device
        1. Example
      5. 9.3.5 Volume Control
        1. DAC Digital Gain Control
          1. Emergency Volume Ramp Down
      6. 9.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 9.3.7 Error Handling and Protection Suite
        1. Device Overtemperature Protection
        2. SPK_OUTxx Overcurrent Protection
        3. DC Offset Protection
        4. Internal VAVDD Undervoltage-Error Protection
        5. Internal VPVDD Undervoltage-Error Protection
        6. Internal VPVDD Overvoltage-Error Protection
        7. External Undervoltage-Error Protection
        8. Internal Clock Error Notification (CLKE)
      8. 9.3.8 GPIO Port and Hardware Control Pins
      9. 9.3.9 I2C Communication Port
        1. Slave Address
        2. Register Address Auto-Increment Mode
        3. Packet Protocol
        4. Write Register
        5. Read Register
        6. DSP Book, Page, and Register Update
          1. Book and Page Change
          2. Swap Flag
          3. Example Use
    4. 9.4 Device Functional Modes
      1. 9.4.1 Serial Audio Port Operating Modes
      2. 9.4.2 Communication Port Operating Modes
      3. 9.4.3 Speaker Amplifier Operating Modes
        1. Stereo Mode
        2. Mono Mode
        3. Master and Slave Mode Clocking for Digital Serial Audio Port
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 External Component Selection Criteria
      2. 10.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 10.1.3 Amplifier Output Filtering
      4. 10.1.4 Programming the TAS5782M
        1. Resetting the TAS5782M Registers and Modules
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
        1. Design Requirements
        2. Detailed Design Procedure
          1. Step One: Hardware Integration
          2. Step Two: System Level Tuning
          3. Step Three: Software Integration
        3. Application Curves
      2. 10.2.2 Mono (PBTL) Systems
        1. Design Requirements
        2. Detailed Design Procedure
          1. Step One: Hardware Integration
          2. Step Two: System Level Tuning
          3. Step Three: Software Integration
        3. Application Specific Performance Plots for Mono (PBTL) Systems
      3. 10.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. Advanced 2.1 System (Two TAS5782M devices)
        2. Design Requirements
        3. Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 DVDD Supply
      2. 11.1.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. Device, Copper, and Component Layout
        2. Stencil Pattern
          1. PCB footprint and Via Arrangement
            1. Solder Stencil
    2. 12.2 Layout Example
      1. 12.2.1 2.0 (Stereo BTL) System
      2. 12.2.2 Mono (PBTL) System
      3. 12.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
  13. 13Register Maps
    1. 13.1 Registers - Page 0
      1. 13.1.1  Register 1 (0x01)
      2. 13.1.2  Register 6 (0x06)
      3. 13.1.3  Register 7 (0x07)
      4. 13.1.4  Register 8 (0x08)
      5. 13.1.5  Register 9 (0x09)
      6. 13.1.6  Register 12 (0x0C)
      7. 13.1.7  Register 13 (0x0D)
      8. 13.1.8  Register 14 (0x0E)
      9. 13.1.9  Register 15 (0x0F)
      10. 13.1.10 Register 16 (0x10)
      11. 13.1.11 Register 17 (0x11)
      12. 13.1.12 Register 18 (0x12)
      13. 13.1.13 Register 20 (0x14)
      14. 13.1.14 Register 21 (0x15)
      15. 13.1.15 Register 22 (0x16)
      16. 13.1.16 Register 23 (0x17)
      17. 13.1.17 Register 24 (0x18)
      18. 13.1.18 Register 27 (0x1B)
      19. 13.1.19 Register 28 (0x1C)
      20. 13.1.20 Register 29 (0x1D)
      21. 13.1.21 Register 30 (0x1E)
      22. 13.1.22 Register 32 (0x20)
      23. 13.1.23 Register 33 (0x21)
      24. 13.1.24 Register 34 (0x22)
      25. 13.1.25 Register 37 (0x25)
      26. 13.1.26 Register 40 (0x28)
      27. 13.1.27 Register 41 (0x29)
      28. 13.1.28 Register 42 (0x2A)
      29. 13.1.29 Register 43 (0x2B)
      30. 13.1.30 Register 44 (0x2C)
      31. 13.1.31 Register 59 (0x3B)
      32. 13.1.32 Register 60 (0x3C)
      33. 13.1.33 Register 61 (0x3D)
      34. 13.1.34 Register 62 (0x3E)
      35. 13.1.35 Register 63 (0x3F)
      36. 13.1.36 Register 64 (0x40)
      37. 13.1.37 Register 65 (0x41)
      38. 13.1.38 Register 67 (0x43)
      39. 13.1.39 Register 68 (0x44)
      40. 13.1.40 Register 69 (0x45)
      41. 13.1.41 Register 70 (0x46)
      42. 13.1.42 Register 71 (0x47)
      43. 13.1.43 Register 72 (0x48)
      44. 13.1.44 Register 73 (0x49)
      45. 13.1.45 Register 74 (0x4A)
      46. 13.1.46 Register 75 (0x4B)
      47. 13.1.47 Register 76 (0x4C)
      48. 13.1.48 Register 78 (0x4E)
      49. 13.1.49 Register 79 (0x4F)
      50. 13.1.50 Register 83 (0x53)
      51. 13.1.51 Register 85 (0x55)
      52. 13.1.52 Register 86 (0x56)
      53. 13.1.53 Register 87 (0x57)
      54. 13.1.54 Register 88 (0x58)
      55. 13.1.55 Register 91 (0x5B)
      56. 13.1.56 Register 92 (0x5C)
      57. 13.1.57 Register 93 (0x5D)
      58. 13.1.58 Register 94 (0x5E)
      59. 13.1.59 Register 95 (0x5F)
      60. 13.1.60 Register 108 (0x6C)
      61. 13.1.61 Register 119 (0x77)
      62. 13.1.62 Register 120 (0x78)
    2. 13.2 Registers - Page 1
      1. 13.2.1 Register 1 (0x01)
      2. 13.2.2 Register 2 (0x02)
      3. 13.2.3 Register 6 (0x06)
      4. 13.2.4 Register 7 (0x07)
      5. 13.2.5 Register 9 (0x09)
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Device Nomenclature
      2. 14.1.2 Development Support
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Community Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

General Guidelines for Audio Amplifiers

Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and the layout of the supporting components used around them. The system level performance metrics, including thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all affected by the device and supporting component layout.

Ideally, the guidance provided in the applications section with regard to device and component selection can be followed by precise adherence to the layout guidance shown in Layout Example. These examples represent exemplary baseline balance of the engineering trade-offs involved with laying out the device. These designs can be modified slightly as needed to meet the needs of a given application. In some applications, for instance, solution size can be compromised to improve thermal performance through the use of additional contiguous copper near the device. Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it is recommended to start from the guidance shown in the Layout Example section and work with TI field application engineers or through the E2E community to modify it based upon the application specific goals.

Importance of PVDD Bypass Capacitor Placement on PVDD Network

Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This applies to DVDD, AVDD, CPVDD, and PVDD. However, the capacitors on the PVDD net for the TAS5782M device deserve special attention.

The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as possible. Not only does placing these devices far away from the pins increase the electromagnetic interference in the system, but doing so can also negatively affect the reliability of the device. Placement of these components too far from the TAS5782M device can cause ringing on the output pins that can cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the device. For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD pins than what is shown in the example layouts in the Layout Example section

Optimizing Thermal Performance

Follow the layout examples shown in the Layout Example section of this document to achieve the best balance of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance can be required due to design constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device naturally travels away from the device and into the lower temperature structures around the device.

Device, Copper, and Component Layout

Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures. These tips should be followed to achieve that goal:

  • Avoid placing other heat producing components or structures near the amplifier (including above or below in the end equipment).
  • If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5782M device and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top and bottom layer.
  • Place the TAS5782M device away from the edge of the PCB when possible to ensure that heat can travel away from the device on all four sides.
  • Avoid cutting off the flow of heat from the TAS5782M device to the surrounding areas with traces or via strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular to the device.
  • Unless the area between two pads of a passive component is large enough to allow copper to flow in between the two pads, orient it so that the narrow end of the passive component is facing the TAS5782M device.
  • Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.

Stencil Pattern

The recommended drawings for the TAS5782M device PCB foot print and associated stencil pattern are shown at the end of this document in the package addendum. Additionally, baseline recommendations for the via arrangement under and around the device are given as a starting point for the PCB design. This guidance is provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all other performance criteria. In elevated ambient temperatures or under high-power dissipation use-cases, this guidance may be too conservative and advanced PCB design techniques may be used to improve thermal performance of the system.


The customer must verify that deviation from the guidance shown in the package addendum, including the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability goals.

PCB footprint and Via Arrangement

The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the shape and position of the copper patterns to which the TAS5782M device will be soldered. This footprint can be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to make sure that the thermal pad, which connects electrically and thermally to the PowerPAD of the TAS5782M device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5782M device has the largest interface possible to move heat from the device to the board.

The via pattern shown in the package addendum provides an improved interface to carry the heat from the device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings) present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the Layout Example section, this interface can benefit from improved thermal performance.


Vias can obstruct heat flow if they are not constructed properly.

More notes on the construction and placement of vias as as follows:

  • Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
  • Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the additional cost of filled vias.
  • The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases, minimum spacing should be determined by the voltages present on the planes surrounding the via and minimized wherever possible.
  • Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding area. This arrangement is shown in the Layout Example section.
  • Ensure that vias do not cut off power current flow from the power supply through the planes on internal layers. If needed, remove some vias that are farthest from the TAS5782M device to open up the current path to and from the device.

Solder Stencil

During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most cases, the aperture for each of the component pads is almost the same size as the pad itself.

However, the thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is called an aperture array, and is shown in the Layout Example section. It is important that the total area of the aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the thermal pad itself.

Layout Example

2.0 (Stereo BTL) System

TAS5782M ss_20_3d_slas988.gif Figure 84. 2.0 (Stereo BTL) 3-D View
TAS5782M ss_20_copper_slas988.gif Figure 85. 2.0 (Stereo BTL) Top Copper View

Mono (PBTL) System

TAS5782M ss_mono_3d_slas988.gif Figure 86. Mono (PBTL) 3-D View
TAS5782M ss_mono_copper_slas988.gif Figure 87. Mono (PBTL) Top Copper View

2.1 (Stereo BTL + Mono PBTL) Systems

TAS5782M ss_21_3d_slas988.gif Figure 88. 2.1 (Stereo BTL + Mono PBTL) 3-D View
TAS5782M ss_21_copper_slas988.gif Figure 89. 2.1 (Stereo BTL + Mono PBTL) Top Copper View