SLASEX7A June   2021  – December 2021 TAS5828M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 6.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 6.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 6.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port – Clock Rates
      4. 8.3.4 Clock Halt Auto-recovery
      5. 8.3.5 Sample Rate on the Fly Change
      6. 8.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 8.3.7 Digital Audio Processing
      8. 8.3.8 Class D Audio Amplifier
        1. 8.3.8.1 Speaker Amplifier Gain Select
        2. 8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Software Control
      2. 8.4.2 Speaker Amplifier Operating Modes
        1. 8.4.2.1 BTL Mode
        2. 8.4.2.2 PBTL Mode
      3. 8.4.3 Low EMI Modes
        1. 8.4.3.1 Spread Spectrum
        2. 8.4.3.2 Channel to Channel Phase Shift
        3. 8.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 8.4.3.3.2 Phase Synchronization With GPIO
      4. 8.4.4 Thermal Foldback
      5. 8.4.5 Device State Control
      6. 8.4.6 Device Modulation
        1. 8.4.6.1 BD Modulation
        2. 8.4.6.2 1SPW Modulation
        3. 8.4.6.3 Hybrid Modulation
    5. 8.5 Programming and Control
      1. 8.5.1 I2 C Serial Communication Bus
      2. 8.5.2 Hardware Control Mode
      3. 8.5.3 I2 C Target Address
        1. 8.5.3.1 Random Write
        2. 8.5.3.2 Sequential Write
        3. 8.5.3.3 Random Read
        4. 8.5.3.4 Sequential Read
        5. 8.5.3.5 DSP Memory Book, Page and BQ update
        6. 8.5.3.6 Checksum
          1. 8.5.3.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 8.5.3.6.2 Exclusive or (XOR) Checksum
      4. 8.5.4 Control via Software
        1. 8.5.4.1 Startup Procedures
        2. 8.5.4.2 Shutdown Procedures
      5. 8.5.5 Protection and Monitoring
        1. 8.5.5.1 Overcurrent Limit (Cycle-By-Cycle)
        2. 8.5.5.2 Overcurrent Shutdown (OCSD)
        3. 8.5.5.3 DC Detect Error
        4. 8.5.5.4 Overtemperature Shutdown (OTSD)
        5. 8.5.5.5 PVDD Overvoltage and Undervoltage Error
        6. 8.5.5.6 PVDD Drop Detection
        7. 8.5.5.7 Clock Fault
    6. 8.6 Register Maps
      1. 8.6.1 CONTROL PORT Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor Selections
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
      5. 9.2.5 Advanced 2.1 System (Two TAS5828M Devices)
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAD|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.2 Hardware Control Mode

For the system which does not require the advanced flexiblity of the I2C registers control or does not have an avaliable I2C host controller, the TAS5828M can be used in Hardware Control Mode. Then the device operates in Hardware mode default configurations and any change is accomplished via the Hardware control pins. The audio performance between Hardware and Software Control mode with same configuration is identical, however more features are accessible under Software Control Mode through registers.

Several I/O's on the TAS5828M need to be took into consideration during schematic design for desired startup settings. The method going into Hardware Control Mode is to pull high HW_MODE pin13 to DVDD.

The TAS5828M default Hardware configuration with optimized audio, thermal and BOM is BTL mode, 768-kHz switching frequency, 1 SPW mode, 175 kHz Class D amplifier loop bandwidth, 29.5 Vp/FS analog gain, CBC threshold with 80% of OCP threshold. It requires the HW_SEL0 pin 5 and HW_SEL1 pin 6 directly tied low GND.

Table 8-5 Hardware Control - HW_SEL0 Pin5
Pin ConfigurationAnalog GainH-Bridge Output Configuration
0 Ω to GND29.5 VP/FSBTL
1 kΩ to GND20.9 VP/FSBTL
4.7 kΩ to GND14.7 VP/FSBTL
15 kΩ to GND7.4 VP/FSBTL
33 kΩ to DVDD7.4 VP/FSPBTL
6.8 kΩ to DVDD14.7 VP/FSPBTL
1.5 kΩ to DVDD20.9 VP/FSPBTL
0 Ω to DVDD29.5 VP/FSPBTL
Table 8-6 Hardware Control - HW_SEL1 Pin6
Pin ConfigurationFSW&Class D Loop BandwidthCycle By Cycle Current Limit Threshold Spread SpectrumModulation
0 Ω to GND768 kHz FSW, 175 kHz BWCBC Threshold = 80% OCPDisable1SPW
1 kΩ to GND768 kHz FSW, 175 kHz BWCBC DisableDisable1SPW
4.7 kΩ to GND768 kHz FSW, 175 kHz BWCBC Threshold = 40% OCPDisable1SPW
15 kΩ to GND768 kHz FSW, 175 kHz BWCBC Threshold = 60% OCPDisable1SPW
33 kΩ to DVDD480 kHz FSW, 100 kHz BWCBC DisableEnableBD
6.8 kΩ to DVDD480 kHz FSW, 100 kHz BWCBC Threshold = 80% OCPEnableBD
1.5 kΩ to DVDD480 kHz FSW, 100 kHz BWCBC Threshold = 40% OCPEnableBD
0 Ω to DVDD480 kHz FSW, 100 kHz BWCBC Threshold = 60% OCPEnableBD

Example 1:

BTL Mode, FSW = 768 kHz, 1 SPW Modulation, 175 kHz Loop Bandwidth, CBC Threshold = 80% OCP, Analog Gain = 29.5 VP/FS, Spread spectrum disable.

Figure 8-10 Typical Hardware Control Mode Application Schematic-BTL Mode

Example 2:

PBTL Mode, FSW = 768 kHz, 1 SPW Modulation, 175 kHz Loop Bandwidth, CBC Threshold = 80% OCP, Analog Gain = 29.5 VP/FS, Spread spectrum disable.

Figure 8-11 Typical Hardware Control Mode Application Schematic-PBTL Mode