SLASEX7A Data sheet

SLASEX7A June 2021 – December 2021 TAS5828M

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DAD|32

Thermal pad, mechanical data (Package|Pins)

DAD|32
- PPTD344A

Orderable Information

8.6.1 CONTROL PORT Registers

Table 8-8 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in Table 8-8 should be considered as reserved locations and the register contents should not be modified.

Table 8-8 CONTROL PORT Registers

Offset	Acronym	Register Name	Section
1h	RESET_CTRL	Register 1	Go
2h	DEVICE_CTRL1	Register 2	Go
3h	DEVICE_CTRL2	Register 3	Go
4h	PVDD_DROP_DETECTION_CTRL1	Register 4	Section 8.6.1.4
5h	PVDD_DROP_DETECTION_CTRL2	Register 5	Section 8.6.1.5
Fh	I2C_PAGE_AUTO_INC	Register 15	Go
28h	SIG_CH_CTRL	Register 40	Go
29h	CLOCK_DET_CTRL	Register 41	Go
30h	SDOUT_SEL	Register 48	Go
31h	I2S_CTRL	Register 49	Go
33h	SAP_CTRL1	Register 51	Go
34h	SAP_CTRL2	Register 52	Go
35h	SAP_CTRL3	Register 53	Go
37h	FS_MON	Register 55	Go
38h	BCK (SCLK)_MON	Register 56	Go
39h	CLKDET_STATUS	Register 57	Go
40h	DSP_PGM_MODE	Register 64	Section 8.6.1.17
46h	DSP_CTRL	Register 70	Go
4Ch	DIG_VOL	Register 76	Go
4Eh	DIG_VOL_CTRL1	Register 78	Go
4Fh	DIG_VOL_CTRL2	Register 79	Go
50h	AUTO_MUTE_CTRL	Register 80	Go
51h	AUTO_MUTE_TIME	Register 81	Go
53h	ANA_CTRL	Register 83	Go
54h	AGAIN	Register 84	Go
5Eh	PVDD_ADC	Register 94	Go
60h	GPIO_CTRL	Register 96	Go
61h	GPIO1_SEL	Register 97	Go
62h	GPIO2_SEL	Register 98	Go
63h	GPIO0_SEL	Register 99	Go
64h	GPIO_INPUT_SEL	Register 100	Go
65h	GPIO_OUT	Register 101	Go
66h	GPIO_OUT_INV	Register 102	Go
67h	DIE_ID	Register 103	Go
68h	POWER_STATE	Register 104	Go
69h	AUTOMUTE_STATE	Register 105	Go
6Ah	PHASE_CTRL	Register 106	Go
6Bh	SS_CTRL0	Register 107	Go
6Ch	SS_CTRL1	Register 108	Go
6Dh	SS_CTRL2	Register 109	Go
6Eh	SS_CTRL3	Register 110	Go
6Fh	SS_CTRL4	Register 111	Go
70h	CHAN_FAULT	Register 112	Go
71h	GLOBAL_FAULT1	Register 113	Go
72h	GLOBAL_FAULT2	Register 114	Go
73h	WARNING	Register 115	Go
74h	PIN_CONTROL1	Register 116	Go
75h	PIN_CONTROL2	Register 117	Go
76h	MISC_CONTROL	Register 118	Go
77h	CBC_CONTROL	Register 119	Go
78h	FAULT_CLEAR	Register 120	Go

Complex bit access types are encoded to fit into small table cells. Table 8-9 shows the codes that are used for access types in this section.

Table 8-9 CONTROL PORT Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

][l.,

8.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]

RESET_CTRL is shown in Figure 8-18 and described in Table 8-10.

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Figure 8-18 RESET_CTRL Register

7	6	5	4	3	2	1	0
RESERVED			RST_MOD	RESERVED			RST_REG
R/W			W	R			W

Table 8-10 RESET_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4	RST_DIG_CORE	W	0	WRITE CLEAR BIT Reset DIG_CORE WRITE CLEAR BIT Reset Full Digital Core. This bit resets the Full Digital Signal Path (Include DSP coefficient RAM and I2C Control Port Registers), Since the DSP is also reset, the coeffient RAM content is also cleared by the DSP. 0: Normal 1: Reset Full Digital Signal Path
3-1	RESERVED	R	000	This bit is reserved
0	RST_REG	W	0	WRITE CLEAR BIT Reset Registers This bit resets the mode registers back to their initial values. Only reset Control Port Registers, The RAM content is not cleared. 0: Normal 1: Reset I²C Control Port Registers

8.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]

DEVICE_CTRL_1 is shown in Figure 8-19 and described in Table 8-11.

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Figure 8-19 DEVICE_CTRL_1 Register

7	6	5	4	3	2	1	0
RESERVED	FSW_SEL			RESERVED	DAMP_PBTL	DAMP_MOD
R/W	R/W			R/W	R/W	R/W

Table 8-11 DEVICE_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-4	FSW_SEL	R/W	000	SELECT FSW 000:384K 010:480K 011:576K 100:768K 001:Reserved 101:Reserved 110:Reserved 111:Reserved
3	RESERVED	R/W	0	This bit is reserved
2	DAMP_PBTL	R/W	0	0: SET DAMP TO BTL MODE 1:SET DAMP TO PBTL MODE
1-0	DAMP_MOD	R/W	00	00:BD MODE 01:1SPW MODE 10:HYBRID MODE

8.6.1.3 DEVICE_CTRL2 Register (Offset = 3h) [reset = 0x10]

DEVICE_CTRL2 is shown in Figure 8-20 and described in Table 8-12.

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Figure 8-20 DEVICE_CTRL2 Register

7	6	5	4	3	2	1	0
RESERVED			DIS_DSP	MUTE_LEFT	RESERVED	CTRL_STATE
R/W			R/W	R/W	R/W	R/W

Table 8-12 DEVICE_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4	DIS_DSP	R/W	1	DSP reset When the bit is made 0, DSP starts powering up and send out data. This needs to be made 0 only after all the input clocks are settled so that DMA channels do not go out of sync. 0: Normal operation 1: Reset the DSP
3	MUTE	R/W	0	Mute both Left and Right Channel This bit issues soft mute request for both left and right channel. The volume is smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute
2	RESERVED	R/W	0	This bit is reserved
1-0	CTRL_STATE	R/W	00	device state control register 00: Deep Sleep 01: Sleep 10: Hiz, 11: PLAY

8.6.1.4 PVDD_DROP_DETECTION_CTRL1 Register (Offset = 4h) [reset = 0x00]

PVDD_DROP_DETECTION_CTRL1 is shown in Figure 8-21 and described in Table 8-13.

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Figure 8-21 PVDD_DROP_DETECTION_CTRL1 Register

7	6	5	4	3	2	1	0
RESERVED				PVDD_DROP_DET_SEQUENCE	PVDD_DROP_DET_AVE_SAMPLES		PVDD_DROP_DET_BYPASS
R/W				R/W	R/W		R/W

Table 8-13 PVDD_DROP_DETECTION_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	000	This bit is reserved
3	PVDD_DROP_DET_State_Control	R/W	0	This bit controls whether device automatically set into Hiz or still play once PVDD drop detection happens. 0: The device keeps in play mode even PVDD drops configured threshold 1: The device goes into Hiz once PVDD drops configured threshold
2-1	PVDD_DROP_DET_AVE_SAMPLES	R/W	00	PVDD sense average samples for drop detection This bit is used to set PVDD voltage sense average samples for drop detection. 00: 1 sample - cycle by cycle, no average 01: 16 samples 10: 32 samples 11: 64 samples
0	PVDD_DROP_DET_Enable	R/W	0	PVDD drop detection Enable This bit controls enable or bypass PVDD drop detection. 0: Bypass PVDD drop detection 1: Enable PVDD drop detection

8.6.1.5 PVDD_DROP_DETECTION_CTRL2 Register (Offset = 5h) [reset = 0x44]

PVDD_DROP_DETECTION_CTRL2 is shown in Figure 8-22 and described in Table 8-14.

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Figure 8-22 PVDD_DROP_DETECTION_CTRL2 Register

7	6	5	4	3	2	1	0
PVDD Drop Detection Voltage Threshold
R/W

Table 8-14 PVDD_DROP_DETECTION_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PVDD Drop Detection Voltage Threshold	R/W	00000000	This bit is used to set PVDD Drop Detection Threshold. The radio to 0xFFh equals to full scale voltage 30V. For example, 8V threshold: 8V/30V = 0x44h/0xFFh. PVDD Drop Threshold is configured as: 00: 0V 01: 0.117V ... 44: 8V ... FF: 30V

8.6.1.6 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]

I2C_PAGE_AUTO_INC is shown in Figure 8-23 and described in Table 8-15.

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Figure 8-23 I2C_PAGE_AUTO_INC Register

7	6	5	4	3	2	1	0
RESERVED				PAGE_AUTOINC_REG	RESERVED
R/W				R/W	R/W

Table 8-15 I2C_PAGE_AUTO_INC Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	This bit is reserved
3	PAGE_AUTOINC_REG	R/W	0	Page auto increment disable Disable page auto increment mode. for non -zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part. 0: Enable Page auto increment 1: Disable Page auto increment
2-0	RESERVED	R/W	000	This bit is reserved

8.6.1.7 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]

SIG_CH_CTRL is shown in Figure 8-24 and described in Table 8-16.

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Figure 8-24 SIG_CH_CTRL Register

7	6	5	4	3	2	1	0
SCLK_RATIO_CONFIGURE				FSMODE	RESERVED
R/W				R/W	R/W

Table 8-16 SIG_CH_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	SCLK_RATIO_CONFIGURE	R/W	0000	These bits indicate the configured SCLK ratio, the number of SCLK clocks in one audio frame. Device sets this ratio automatically. 4'b0011:32FS 4'b0101:64FS 4'b0111:128FS 4'b1001:256FS 4'b1011:512FS
3	FSMODE	R/W	0	FS Speed Mode These bits select the FS operation mode, which must be set according to the current audio sampling rate. Need set it manually If the input Fs is 44.1kHz/88.2kHz/176.4kHz. 4 'b0000 Auto detection 4 'b0100 Reserved 4 'b0110 32KHz 4 'b1000 44.1KHz 4 'b1001 48KHz 4'b1010 88.2KHz 4 'b1011 96KHz 4 'b1100 176.4KHz 4 'b1101 192KHz Others Reserved
2-0	RESERVED	R/W	000	This bit is reserved

8.6.1.8 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]

CLOCK_DET_CTRL is shown in Figure 8-25 and described in Table 8-17.

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Figure 8-25 CLOCK_DET_CTRL Register

7	6	5	4	3	2	1	0
RESERVED	DIS_DET_PLL	DIS_DET_SCLK_RANGE	DIS_DET_FS	DIS_DET_SCLK	DIS_DET_MISS	RESERVED	RESERVED
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Table 8-17 CLOCK_DET_CTRL Register Field Descriptions

Bit	Field	Type	Description
7	RESERVED	R/W	This bit is reserved
6	DIS_DET_PLL	R/W	Ignore PLL overate Detection This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150MHz or an error is reported. When ignored, a PLL overrate error does not cause a clock error. 0: Regard PLL overrate detection 1: Ignore PLL overrate detection
5	DIS_DET_SCLK_RANGE	R/W	Ignore BCK Range Detection This bit controls whether to ignore the SCLK range detection. The SCLK must be stable between 256 KHz and 50 MHz or an error is reported. When ignored, a SCLK range error does not cause a clock error. 0: Regard BCK Range detection 1: Ignore BCK Range detection
4	DIS_DET_FS	R/W	Ignore FS Error Detection This bit controls whether to ignore the FS Error detection. When ignored, FS error does not cause a clock error.But CLKDET_STATUS reports fs error. 0: Regard FS detection 1: Ignore FS detection
3	DIS_DET_SCLK	R/W	Ignore SCLK Detection This bit controls whether to ignore the SCLK detection against LRCK. The SCLK must be stable between 32FS and 512FS inclusive or an error is reported. When ignored, a SCLK error does not cause a clock error. 0: Regard SCLK detection 1: Ignore SCLK detection
2	DIS_DET_MISS	R/W	Ignore SCLK Missing Detection This bit controls whether to ignore the SCLK missing detection. When ignored, an SCLK missing does not cause a clock error. 0: Regard SCLK missing detection 1: Ignore SCLKmissing detection
1	RESERVED	R/W	This bit is reserved
0	RESERVED	R/W	This bit is reserved

8.6.1.9 SDOUT_SEL Register (Offset = 30h) [reset = 0x00]

SDOUT_SEL is shown in Figure 8-27 and described in Table 8-18.

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Figure 8-26 SDOUT_SEL Register

7	6	5	4	3	2	1	0
RESERVED					RESERVED		SDOUT_SEL
R/W					R/W		R/W

Table 8-18 SDOUT_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0000000	These bits are reserved
0	SDOUT_SEL	R/W	0	SDOUT Select. This bit selects what is being output as SDOUT pin. 0: SDOUT is the DSP output (post-processing) 1: SDOUT is the DSP input (pre-processing)

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

0000000

These bits are reserved

SDOUT_SEL

R/W

SDOUT Select. This bit selects what is being output as SDOUT pin.

0: SDOUT is the DSP output (post-processing)

1: SDOUT is the DSP input (pre-processing)

8.6.1.10 I2S_CTRL Register (Offset = 31h) [reset = 0x00]

I2S_CTRL is shown in Figure 8-27 and described in Table 8-19.

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Figure 8-27 I2S_CTRL Register

7	6	5	4	3	2	1	0
RESERVED		SCLK_INV	RESERVED	RESERVED	RESERVED		RESERVED
R/W		R/W	R/W	R	R		R/W

Table 8-19 I2S_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	This bit is reserved
5	SCLK_INV	R/W	0	SCLK Polarity This bit sets the inverted SCLK mode. In inverted SCLK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the SCLK. Normally they are assumed to be aligned to the falling edge of theSCLK 0: Normal SCLKmode 1: Inverted SCLK mode
4	RESERVED	R/W	0	This bit is reserved
3	RESERVED	R	0	This bit is reserved
2-1	RESERVED	R	00	These bits are reserved
0	RESERVED	R/W	0	This bit is reserved

8.6.1.11 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]

SAP_CTRL1 is shown in Figure 8-28 and described in Table 8-20.

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Figure 8-28 SAP_CTRL1 Register

7	6	5	4	3	2	1	0
I2S_SHIFT_MSB	RESERVED	DATA_FORMAT		I2S_LRCLK_PULSE		WORD_LENGTH
R/W	R/W	R/W		R/W		R/W

Table 8-20 SAP_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	I2S_SHIFT_MSB	R/W	0	I2S Shift MSB
6	RESERVED	R/W	0	This bit is reserved
5-4	DATA_FORMAT	R/W	00	I2S Data Format These bits control both input and output audio interface formats for DAC operation. 00: I2S 01: TDM/DSP 10: RTJ 11: LTJ
3-2	I2S_LRCLK_PULSE	R/W	00	01: LRCLK pulse < 8 SCLK
1-0	WORD_LENGTH	R/W	10	I2S Word Length These bits control both input and output audio interface sample word lengths for DAC operation. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits

8.6.1.12 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]

SAP_CTRL2 is shown in Figure 8-29 and described in Table 8-21.

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Figure 8-29 SAP_CTRL2 Register

7	6	5	4	3	2	1	0
I2S_SHIFT
R/W

Table 8-21 SAP_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	I2S_SHIFT	R/W	00000000	I2S Shift LSB These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of SCLK from the starting (MSB) of audio frame to the starting of the desired audio sample. MSB [8] locates in Section 8.6.1.11 000000000: offset = 0 SCLK (no offset) 000000001: ofsset = 1 SCLK 000000010: offset = 2 SCLKs and 111111111: offset = 512 SCLKs

8.6.1.13 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]

SAP_CTRL3 is shown in Figure 8-30 and described in Table 8-22.

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Figure 8-30 SAP_CTRL3 Register

7	6	5	4	3	2	1	0
RESERVED		LEFT_DAC_DPATH		RESERVED		RIGHT_DAC_DPATH
R/W		R/W		R/W		R/W

Table 8-22 SAP_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	These bits are reserved
5-4	LEFT_DAC_DPATH	R/W	01	Left DAC Data Path. These bits control the left channel audio data path connection. 00: Zero data (mute) 01: Left channel data 10: Right channel data 11: Reserved (do not set)
3-2	RESERVED	R/W	00	These bits are reserved
1-0	RIGHT_DAC_DPATH	R/W	01	Right DAC Data Path. These bits control the right channel audio data path connection. 00: Zero data (mute) 01: Right channel data 10: Left channel data 11: Reserved (do not set)

8.6.1.14 FS_MON Register (Offset = 37h) [reset = 0x00]

FS_MON is shown in Figure 8-31 and described in Table 8-23.

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Figure 8-31 FS_MON Register

7	6	5	4	3	2	1	0
RESERVED		SCLK_RATIO_HIGH		FS
R/W		R		R

Table 8-23 FS_MON Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	This bit is reserved
5-4	SCLK_RATIO_HIGH	R	00	2 msbs of detected SCLK ratio
3-0	FS	R	0000	These bits indicate the currently detected audio sampling rate. 4 'b0000 FS Error 4 'b0100 16KHz 4 'b0110 32KHz 4 'b1000 Reserved 4 'b1001 48KHz 4 'b1011 96KHz 4 'b1101 192KHz Others Reserved

8.6.1.15 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]

BCK_MON is shown in Figure 8-32 and described in Table 8-24.

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Figure 8-32 BCK (SCLK)_MON Register

7	6	5	4	3	2	1	0
BCLK (SCLK)_RATIO_LOW
R

Table 8-24 BCK_MON Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	BCLK (SCLK)_RATIO_LOW	R	00000000	These bits indicate the currently detected BCK (SCLK) ratio, the number of BCK (SCLK) clocks in one audio frame. BCK (SCLK) = 32 FS~512 FS

Bit

Field

Type

Reset

Description

7-0

BCLK (SCLK)_RATIO_LOW

00000000

These bits indicate the currently detected BCK (SCLK) ratio, the number of BCK (SCLK) clocks in one audio frame.

BCK (SCLK) = 32 FS~512 FS

8.6.1.16 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]

CLKDET_STATUS is shown in Figure 8-33 and described in Table 8-25.

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Figure 8-33 CLKDET_STATUS Register

7	6	5	4	3	2	1	0
RESERVED		DET_STATUS
R/W		R

Table 8-25 CLKDET_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	This bit is reserved
5-0	DET_STATUS	R	000000	bit0: In auto detection mode(reg_fsmode=0),this bit indicated whether the audio sampling rate is valid or not. In non auto detection mode(reg_fsmode!=0), Fs error indicates that configured fs is different with detected fs. Even FS Error Detection Ignore is set, this flag is also asserted. bit1: This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and in the range of 32-512FS to be valid. bit2: This bit indicates whether the SCLK is missing or not. bit3:This bit indicates whether the PLL is locked or not. The PLL is reported as unlocked when it is disabled. bits4:This bit indicates whether the PLL is overrate bits5:This bit indicates whether the SCLK is overrate or underrate

8.6.1.17 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]

DSP_PGM_MODE is shown in Figure 8-34 and described in Table 8-26.

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Figure 8-34 DSP_PGM_MODE Register

7	6	5	4	3	2	1	0
RESERVED			CH1_HIZ	CH2_HIZ	MODE_SEL
R/W			R/W

Table 8-26 DSP_PGM_MODE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4	CH1_HIZ	R/W	0	Hi-Z Mode Channel-1 Stops output switching and sets channel-1 to Hi-Z mode. 0: Normal Operation 1: Hi-Z state
3	CH2_HIZ	R/W	0	Hi-Z Mode Channel-2 Stops output switching and sets channel-2 to Hi-Z mode. 0: Normal Operation 1: Hi-Z state
2-0	MODE_SEL	R/W	00001	DSP Program Selection These bits select the DSP program to use for audio processing. 000 => ram mode 001 => rom mode 1

8.6.1.18 DSP_CTRL Register (Offset = 46h) [reset = 0x01]

DSP_CTRL is shown in Figure 8-35 and described in Table 8-27.

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Figure 8-35 DSP_CTRL Register

7	6	5	4	3	2	1	0
RESERVED			USER_DEFINED_PROCESSING_RATE		RESERVED	BOOT_FROM_IRAM	USE_DEFAULT_COEFFS
R/W			R/W		R	R/W	R/W

Table 8-27 DSP_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4-3	USER_DEFINED_PROCESSING_RATE	R/W	00	00:input 01:48k 10:96k 11:192k
2	RESERVED	R	0	This bit is reserved
1	RESERVED	R	0	This bit is reserved
0	RESERVED	R/W	1	This bit is reserved

8.6.1.19 DIG_VOL Register (Offset = 4Ch) [reset = 30h]

DIG_VOL is shown in Figure 8-36 and described in Table 8-28.

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Figure 8-36 DIG_VOL Register

7	6	5	4	3	2	1	0
PGA_LEFT
R/W

Table 8-28 DIG_VOL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PGA	R/W	00110000	Digital Volume These bits control both left and right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. 00000000: +24.0 dB 00000001: +23.5 dB ........ and 00101111: +0.5 dB 00110000: 0.0 dB 00110001: -0.5 dB ....... 11111110: -103 dB 11111111: Mute

8.6.1.20 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL1 is shown in Figure 8-37 and described in Table 8-29.

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Figure 8-37 DIG_VOL_CTRL1 Register

7	6	5	4	3	2	1	0
PGA_RAMP_DOWN_SPEED		PGA_RAMP_DOWN_STEP		PGA_RAMP_UP_SPEED		PGA_RAMP_UP_STEP
R/W		R/W		R/W		R/W

Table 8-29 DIG_VOL_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PGA_RAMP_DOWN_SPEED	R/W	00	Digital Volume Normal Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	PGA_RAMP_DOWN_STEP	R/W	11	Digital Volume Normal Ramp Down Step These bits control the step of the digital volume updates when the volume is ramping down. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-2	PGA_RAMP_UP_SPEED	R/W	00	Digital Volume Normal Ramp Up Frequency These bits control the frequency of the digital volume updates when the volume is ramping up. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly restore the volume (Instant unmute)
1-0	PGA_RAMP_UP_STEP	R/W	11	Digital Volume Normal Ramp Up Step These bits control the step of the digital volume updates when the volume is ramping up. 00: Increment by 4 dB for each updat e 01: Increment by 2 dB for each update 10: Increment by 1 dB for each update 11: Increment by 0.5 dB for each update

8.6.1.21 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]

DIG_VOL_CTRL2 is shown in Figure 8-38 and described in Table 8-30.

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Figure 8-38 DIG_VOL_CTRL2 Register

7	6	5	4	3	2	1	0
FAST_RAMP_DOWN_SPEED		FAST_RAMP_DOWN_STEP		RESERVED
R/W		R/W		R/W

Table 8-30 DIG_VOL_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	FAST_RAMP_DOWN_SPEED	R/W	00	Digital Volume Emergency Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	FAST_RAMP_DOWN_STEP	R/W	11	Digital Volume Emergency Ramp Down Step These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-0	RESERVED	R/W	0000	This bit is reserved

8.6.1.22 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x00]

AUTO_MUTE_CTRL is shown in Figure 8-39 and described in Table 8-31.

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Figure 8-39 AUTO_MUTE_CTRL Register

7	6	5	4	3	2	1	0
RESERVED					REG_AUTO_MUTE_CTRL
R/W					R/W

Table 8-31 AUTO_MUTE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	00000	This bit is reserved
2-0	REG_AUTO_MUTE_CTRL	R/W	000	bit0: 0: Disable left channel auto mute 1: Enable left channel auto mute bit1: 0: Disable right channel auto mute 1: Enable right channel auto mute bit2: 0: Auto mute left channel and right channel independently. 1: Auto mute left and right channels only when both channels are about to be auto muted.

8.6.1.23 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]

AUTO_MUTE_TIME is shown in Figure 8-40 and described in Table 8-32.

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Figure 8-40 AUTO_MUTE_TIME Register

7	6	5	4	3	2	1	0
RESERVED	AUTOMUTE_TIME_LEFT			RESERVED	AUTOMUTE_TIME_RIGHT
R/W	R/W			R/W	R/W

Table 8-32 AUTO_MUTE_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-4	AUTOMUTE_TIME_LEFT	R/W	000	Auto Mute Time for Left Channel These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and scales with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec
3	RESERVED	R/W	0	This bit is reserved
2-0	AUTOMUTE_TIME_RIGHT	R/W	000	Auto Mute Time for Right Channel These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and scales with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec

8.6.1.24 ANA_CTRL Register (Offset = 53h) [reset = 0h]

ANA_CTRL is shown inFigure 8-41 and described in Table 8-33

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Figure 8-41 ANA_CTRL Register

7	6	5	4	3	2	1	0
AMUTE_DLY
R/W

Table 8-33 ANA_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-5	Class D bandwidth control	R/W	00	00: 100kHz 01: 80kHz 10: 120kHz 11:175kHz With Fsw=384kHz, 100kHz bandwidth is selected for high audio performance. With Fsw=768kHz, 175kHz bandwidth should be selected for high audio performance.
4-1	RESERVED	R/W	0000	These bits are reserved
0	L and R PWM output phase control	R/W	0	0: out of phase 1: in phase

8.6.1.25 AGAIN Register (Offset = 54h) [reset = 0x00]

AGAIN is shown in Figure 8-42 and described in Table 8-34.

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Figure 8-42 AGAIN Register

7	6	5	4	3	2	1	0
RESERVED			ANA_GAIN
R/W			R/W

Table 8-34 AGAIN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4-0	ANA_GAIN	R/W	00000	Analog Gain Control This bit controls the analog gain. 00000: 0 dB (29.5V peak voltage) 00001:-0.5db 11111: -15.5 dB

8.6.1.26 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]

PVDD_ADC is shown in Figure 8-43 and described in Table 8-35.

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Figure 8-43 PVDD_ADC Register

7	6	5	4	3	2	1	0
ADC_DATA_OUT
R

Table 8-35 PVDD_ADC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

PVDD_ADC[7:0]

00000000

PVDD Voltage = PVDD_ADC[7:0] / 8.428 (V)

223: 26.45V

222: 26.34V

221:26.22V

...

39: 4.63V

38: 4.51V

37: 4.39V

8.6.1.27 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]

GPIO_CTRL is shown in Figure 8-44 and described in Table 8-36.

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Figure 8-44 GPIO_CTRL Register

7	6	5	4	3	2	1	0
RESERVED					GPIO0_OE	GPIO2_OE	GPIO1_OE
R/W					R/W	R/W	R/W

Table 8-36 GPIO_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	0000	This bit is reserved
2	GPIO0_OE	R/W	0	GPIO2 Output Enable. This bit sets the direction of the GPIO0 pin 0: GPIO0 is input 1: GPIO0 is output
1	GPIO2_OE	R/W	0	GPIO2 Output Enable This bit sets the direction of the GPIO2 pin 0: GPIO2 is input 1: GPIO2 is output
0	GPIO1_OE	R/W	0	GPIO1 Output Enable This bit sets the direction of the GPIO1 pin 0: GPIO1 is input 1: GPIO1 is output

8.6.1.28 GPIO1_SEL Register (Offset = 61h) [reset = 0x00]

GPIO1_SEL is shown in Figure 8-45 and described in Table 8-37.

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Figure 8-45 GPIO1_SEL Register

7	6	5	4	3	2	1	0
RESERVED				GPIO1_SEL
R/W				R/W

Table 8-37 GPIO1_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	This bit is reserved
3-0	GPIO1_SEL	R/W	0000	0000: off (low) 1000: GPIO1 as WARNZ output 1001: GPIO1 as Serial audio interface data output (SDOUT) 1011: GPIO1 as FAULTZ output 1100: GPIO1 as PVDD Drop Detection Flag 1101: GPIO1 as Class-H

8.6.1.29 GPIO2_SEL Register (Offset = 62h) [reset = 0x00]

GPIO2_SEL is shown in Figure 8-46 and described in Table 8-38.

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Figure 8-46 GPIO2_SEL Register

7	6	5	4	3	2	1	0
RESERVED				GPIO2_SEL
R/W				R/W

Table 8-38 GPIO2_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	This bit is reserved
3-0	GPIO2_SEL	R/W	0000	0000: off (low) 1000: GPIO2 as WARNZ output 1001: GPIO2 as Serial audio interface data output (SDOUT) 1011: GPIO2 as FAULTZ output 1100: GPIO2 as PVDD Drop Detection Flag 1101: GPIO2 as Class-H

8.6.1.30 GPIO0_SEL Register (Offset = 63h) [reset = 0x00]

GPIO0_SEL is shown in Figure 8-47 and described in Table 8-39.

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Figure 8-47 GPIO0_SEL Register

7	6	5	4	3	2	1	0
RESERVED				GPIO0_SEL
R/W				R/W

Table 8-39 GPIO0_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	This bit is reserved
3-0	GPIO0_SEL	R/W	0000	0000: off (low) 1000: GPIO0 as WARNZ output 1001: GPIO0 as Serial audio interface data output (SDOUT) 1011: GPIO0 as FAULTZ output 1100: GPIO0 as PVDD Drop Detection Flag 1101: GPIO0 as Class-H

8.6.1.31 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]

GPIO_INPUT_SEL is shown in Figure 8-48 and described in Table 8-40.

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Figure 8-48 GPIO_INPUT_SEL Register

7	6	5	4	3	2	1	0
GPIO_SPI_MISO_SEL		GPIO_PHASE_SYNC_SEL		GPIO_RESETZ_SEL		GPIO_MUTEZ_SEL
R/W		R/W		R/W		R/W

Table 8-40 GPIO_INPUT_SEL Register Field Descriptions

Bit	Field	Type	Description
7-6	GPIO_SPI_MISO_SEL	R/W	00: N/A 01: GPIO1 10: GPIO2 11: GPIO0
5-4	GPIO_PHASE_SYNC_SEL	R/W	00: N/A 01: GPIO1 10: GPIO2 11: GPIO0
3-2	GPIO_RESETZ_SEL	R/W	00: N/A 01: GPIO1 10: GPIO2 11: GPIO0 can not be reset by GPIO reset
1-0	GPIO_MUTEZ_SEL	R/W	00: N/A 01: GPIO1 10: GPIO2 11: GPIO0 MUTEZ pin active-low, output driver is set to HiZ state, Class D amplifier's output stop switching.

8.6.1.32 GPIO_OUT Register (Offset = 65h) [reset = 0x00]

GPIO_OUT is shown in Figure 8-49 and described in Table 8-41.

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Figure 8-49 GPIO_OUT Register

7	6	5	4	3	2	1	0
RESERVED					GPIO_OUT
R/W					R/W

Table 8-41 GPIO_OUT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	00000	This bit is reserved
2-0	GPIO_OUT	R/W	000	bit0: GPIO1 output bit1: GPIO2 output bit2: GPIO0 output

8.6.1.33 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]

GPIO_OUT_INV is shown in Figure 8-50 and described in Table 8-42.

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Figure 8-50 GPIO_OUT_INV Register

7	6	5	4	3	2	1	0
RESERVED					GPIO_OUT
R/W					R/W

Table 8-42 GPIO_OUT_INV Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	00000	This bit is reserved
2-0	GPIO_OUT	R/W	000	bit0: GPIO1 output invert bit1: GPIO2 output invert bit2: GPIO0 output invert

8.6.1.34 DIE_ID Register (Offset = 67h) [reset = 95h]

DIE_ID is shown in Figure 8-51 and described in Table 8-43.

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Figure 8-51 DIE_ID Register

7	6	5	4	3	2	1	0
DIE_ID
R

Table 8-43 DIE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIE_ID	R	10010101	DIE ID

8.6.1.35 POWER_STATE Register (Offset = 68h) [reset = 0x00]

POWER_STATE is shown in Figure 8-52 and described in Table 8-44.

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Figure 8-52 POWER_STATE Register

7	6	5	4	3	2	1	0
STATE_RPT
R

Table 8-44 POWER_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

STATE_RPT

00000000

0: Deep sleep

1: Seep

2: HIZ

3: Play

Others: reserved

8.6.1.36 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]

AUTOMUTE_STATE is shown in Figure 8-53 and described in Table 8-45.

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Figure 8-53 AUTOMUTE_STATE Register

7	6	5	4	3	2	1	0
RESERVED						ZERO_RIGHT_MON	ZERO_LEFT_MON
R						R	R

Table 8-45 AUTOMUTE_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

RESERVED

000000

This bit is reserved

ZERO_RIGHT_MON

This bit indicates the auto mute status for right channel.

0: Not auto muted

1: Auto muted

ZERO_LEFT_MON

This bit indicates the auto mute status for left channel.

0: Not auto muted

1: Auto muted

8.6.1.37 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]

PHASE_CTRL is shown in Figure 8-54 and described in Table 8-46.

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Figure 8-54 PHASE_CTRL Register

7	6	5	4	3	2	1	0
RESERVED				RAMP_PHASE_SEL		PHASE_SYNC_SEL	PHASE_SYNC_EN
R/W				R/W		R/W	R/W

Table 8-46 PHASE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	This bit is reserved
3-2	RAMP_PHASE_SEL	R/W	00	select ramp clock phase when multi devices integrated in one system to reduce EMI and peak supply peak current, it is recomended set all devices the same RAMP frequency and same spread spectrum. it must be set before driving device into PLAY mode if this feature is needed. 2'b00: phase 0 2'b01: phase 1 2'b10: phase 2 2'b11: phase 3 all of above have a 45 degree of phase shift
1	PHASE_SYNC_SEL	R/W	0	ramp phase sync sel, 0: is gpio sync; 1: intenal sync
0	PHASE_SYNC_EN	R/W	0	ramp phase sync enable

8.6.1.38 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]

RAMP_SS_CTRL0 is shown in Figure 8-55 and described in Table 8-47.

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Figure 8-55 SS_CTRL0 Register

7	6	5	4	3	2	1	0
RESERVED	RESERVED	SS_PRE_DIV_SEL	SS_MANUAL_MODE	RESERVED		SS_RDM_EN	SS_TRI_EN
R/W	R/W	R/W	R/W	R/W		R/W	R/W

Table 8-47 RAMP_SS_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6	RESERVED	R/W	0	This bit is reserved
5	SS_PRE_DIV_SEL	R/W	0	Select pll clock divide 2 as source clock in manual mode
4	SS_MANUAL_MODE	R/W	0	Set ramp ss controller to manual mode
3-2	RESERVED	R/W	00	This bit is reserved
1	SS_RDM_EN	R/W	0	Random SS enable
0	SS_TRI_EN	R/W	0	Triangle SS enable

8.6.1.39 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]

SS_CTRL1 is shown in Figure 8-56 and described in Table 8-48.

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Figure 8-56 SS_CTRL1 Register

7	6	5	4	3	2	1	0
RESERVED	SS_RDM_CTRL			SS_TRI_CTRL
R/W	R/W			R/W

Table 8-48 SS_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-4	SS_RDM_CTRL	R/W	000	Add Dither
3-0	SS_TRI_CTRL	R/W	0000	Triangle SS frequency and range control

8.6.1.40 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]

SS_CTRL2 is shown in Figure 8-57 and described in Table 8-49.

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Figure 8-57 SS_CTRL2 Register

7	6	5	4	3	2	1	0
TM_FREQ_CTRL
R/W

Table 8-49 SS_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	TM_FREQ_CTRL	R/W	10100000	Control ramp frequency in manual mode, F=61440000/N

8.6.1.41 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]

SS_CTRL3 is shown in Figure 8-58 and described in Table 8-50.

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Figure 8-58 SS_CTRL3 Register

7	6	5	4	3	2	1	0
TM_DSTEP_CTRL				TM_USTEP_CTRL
R/W				R/W

Table 8-50 SS_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	SS_TM_DSTEP_CTRL	R/W	0001	Control triangle mode spread spectrum fall step in ramp ss manual mode
3-0	SS_TM_USTEP_CTRL	R/W	0001	Control triangle mode spread spectrum rise step in ramp ss manual mode

8.6.1.42 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]

SS_CTRL4 is shown in Figure 8-59 and described in Table 8-51.

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Figure 8-59 SS_CTRL4 Register

7	6	5	4	3	2	1	0
RESERVED	TM_AMP_CTRL		SS_TM_PERIOD_BOUNDRY
R/W	R/W		R/W

Table 8-51 SS_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-5	TM_AMP_CTRL	R/W	01	Control ramp amp ctrl in ramp ss manual model
4-0	SS_TM_PERIOD_BOUNDRY	R/W	00100	Control triangle mode spread spectrum boundary in ramp ss manual mode

8.6.1.43 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CHAN_FAULT is shown in Figure 8-60 and described in Table 8-52.

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Figure 8-60 CHAN_FAULT Register

7	6	5	4	3	2	1	0
RESERVED				CH1_DC_1	CH2_DC_1	CH1_OC_I	CH2_OC_I
R				R	R	R	R

Table 8-52 CHAN_FAULT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0000	This bit is reserved
3	CH1_DC_1	R	0	Left channel DC fault. Once there is a DC fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.
2	CH2_DC_1	R	0	Right channel DC fault. Once there is a DC fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.
1	CH1_OC_I	R	0	Left channel over current fault. Once there is a OC fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.
0	CH2_OC_I	R	0	Right channel over current fault. Once there is a OC fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.

8.6.1.44 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

GLOBAL_FAULT1 is shown in Figure 8-61 and described in Table 8-53.

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Figure 8-61 GLOBAL_FAULT1 Register

7	6	5	4	3	2	1	0
OTP_CRC_ERROR	BQ_WR_ERROR	LOAD_EEPROM_ERROR	RESERVED	RESERVED	CLK_FAULT_I	PVDD_OV_I	PVDD_UV_I
R	R	R	R	R	R	R	R

Table 8-53 GLOBAL_FAULT1 Register Field Descriptions

Bit	Field	Type	Description
7	OTP_CRC_ERROR	R	Indicate OTP CRC check error.
6	BQ_WR_ERROR	R	The recent BQ is written failed
5	LOAD_EEPROM_ERROR	R	0: EEPROM boot load was done successfully 1: EEPROM boot load was done unsuccessfully
4	RESERVED	R	This bit is reserved
3	RESERVED	R	This bit is reserved
2	CLK_FAULT_I	R	Clock fault. Once there is a Clock fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clock fault works with an auto-recovery mode, once the clock error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.
1	PVDD_OV_I	R	PVDD OV fault. Once there is a OV fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.
0	PVDD_UV_I	R	PVDD UV fault. Once there is a UV fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.

8.6.1.45 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

GLOBAL_FAULT2 is shown in Figure 8-62 and described in Table 8-54.

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Figure 8-62 GLOBAL_FAULT2 Register

7	6	5	4	3	2	1	0
RESERVED					CBC_FAULT_CH2_I	CBC_FAULT_CH1_I	OTSD_I
R					R	R	R

Table 8-54 GLOBAL_FAULT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	0000	This bit is reserved
2	CBC_FAULT_CH2_I	R	0	Right channel cycle by cycle over current fault
1	CBC_FAULT_CH1_I	R	0	Left channel cycle by cycle over current fault
0	OTSD_I	R	0	Over temperature shut down fault. Once there is a OT fault, this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Section 8.6.1.51 to 1 or this bit keeps 1.

8.6.1.46 WARNING Register (Offset = 73h) [reset = 0x00]

WARNING is shown in Figure 8-63 and described in Table 8-55.

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Figure 8-63 WARNING Register

7	6	5	4	3	2	1	0
RESERVED		CBCW_CH1_I	CBCW_CH2_I	OTW_LEVEL4_I	OTW_LEVEL3_I	OTW_LEVEL2_I	OTW_LEVEL1_I
R		R	R	R	R	R	R

Table 8-55 WARNING Register Field Descriptions

Bit	Field	Type	Description
7-6	RESERVED	R	This bit is reserved
5	CBCW_CH1_I	R	Left channel cycle by cycle over current warning
4	CBCW_CH2_I	R	Right channel cycle by cycle over current warning
3	OTW_LEVEL4_I	R	Over temperature warning leve4, 146C
2	OTW_LEVEL3_I	R	Over temperature warning leve3, 134C
1	OTW_LEVEL2_I	R	Over temperature warning leve2, 122C
0	OTW_LEVEL1_I	R	Over temperature warning leve1, 112C

8.6.1.47 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]

PIN_CONTROL1 is shown in Figure 8-64 and described in Table 8-56.

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Figure 8-64 PIN_CONTROL1 Register

7	6	5	4	3	2	1	0
MASK_OTSD	MASK_DVDD_UV	MASK_DVDD_OV	MASK_CLK_FAULT	RESERVED	MASK_PVDD_UV	MASK_DC	MASK_OC
R/W	R/W	R/W	R/W	R	R/W	R/W	R/W

Table 8-56 PIN_CONTROL1 Register Field Descriptions

Bit	Field	Type	Description
7	MASK_OTSD	R/W	Mask OTSD fault report
6	MASK_DVDD_UV	R/W	Mask DVDD UV fault report
5	MASK_DVDD_OV	R/W	Mask DVDD OV fault report
4	MASK_CLK_FAULT	R/W	Mask clock fault report
3	RESERVED	R	This bit is reserved
2	MASK_PVDD_UV	R/W	Mask PVDD UV fault report mask PVDD OV fault report
1	MASK_DC	R/W	Mask DC fault report
0	MASK_OC	R/W	Mask OC fault report

8.6.1.48 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]

PIN_CONTROL2 is shown in Figure 8-65 and described in Table 8-57.

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Figure 8-65 PIN_CONTROL2 Register

7	6	5	4	3	2	1	0
CBC_FAULT_LATCH_EN	CBC_WARN_LATCH_EN	CLKFLT_LATCH_EN	OTSD_LATCH_EN	OTW_LATCH_EN	MASK_OTW	MASK_CBCW	MASK_CBC_FAULT
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Table 8-57 PIN_CONTROL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CBC_FAULT_LATCH_EN	R/W	1	Enable CBC fault latch by setting this bit to 1
6	CBC_WARN_LATCH_EN	R/W	1	Enable CBC warning latch by setting this bit to 1
5	CLKFLT_LATCH_EN	R/W	1	Enable clock fault latch by setting this bit to 1
4	OTSD_LATCH_EN	R/W	1	Enable OTSD fault latch by setting this bit to 1
3	OTW_LATCH_EN	R/W	1	Enable OT warning latch by setting this bit to 1
2	MASK_OTW	R/W	0	Mask OT warning report by setting this bit to 1
1	MASK_CBCW	R/W	0	Mask CBC warning report by setting this bit to 1
0	MASK_CBC_FAULT	R/W	0	Mask CBC fault report by setting this bit to 1

8.6.1.49 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]

MISC_CONTROL is shown in Figure 8-66 and described in Table 8-58.

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Figure 8-66 MISC_CONTROL Register

7	6	5	4	3	2	1	0
DET_STATUS_LATCH	RESERVED		OTSD_AUTO_REC_EN	RESERVED
R/W	R/W		R/W	R/W

Table 8-58 MISC_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DET_STATUS_LATCH	R/W	0	1:Latch clock detection status 0:Don't latch clock detection status
6-5	RESERVED	R/W	00	These bits are reserved
4	OTSD_AUTO_REC_EN	R/W	0	OTSD auto recovery enable
3-0	RESERVED	R/W	0000	This bit is reserved

8.6.1.50 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]

CBC_CONTROL is shown in Figure 8-67 and described in Table 8-59.

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Figure 8-67 CBC_CONTROL Register

7	6	5	4	3	2	1	0
RESERVED			CBC_LEVEL_SEL		CBC_EN	CBC_WARN_EN	CBC_FAULT_EN
R/W			R/W		R/W	R/W	R/W

Table 8-59 CBC_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	These bits are reserved
4-3		CBC_LEVEL_SEL	00	This bit sets CBC level, which is percentage to Over-Current Threshold: 00: 80% 10: 60% 01: 40%
2	CBC_EN	R/W	0	Enable CBC function
1	CBC_WARN_EN	R/W	0	Enable CBC warning
0	CBC_FAULT_EN	R/W	0	Enable CBC fault

8.6.1.51 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]

FAULT_CLEAR is shown in Figure 8-68 and described in Table 8-60.

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Figure 8-68 FAULT_CLEAR Register

7	6	5	4	3	2	1	0
ANALOG_FAULT_CLEAR	RESERVED
W	R/W

Table 8-60 FAULT_CLEAR Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ANALOG_FAULT_CLEAR	W	0	WRITE CLEAR BIT once write this bit to 1, device clears analog fault
6-0	RESERVED	R/W	0000000	This bit is reserved