SLASEX7A June   2021  – December 2021 TAS5828M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 6.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 6.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 6.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port – Clock Rates
      4. 8.3.4 Clock Halt Auto-recovery
      5. 8.3.5 Sample Rate on the Fly Change
      6. 8.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 8.3.7 Digital Audio Processing
      8. 8.3.8 Class D Audio Amplifier
        1. 8.3.8.1 Speaker Amplifier Gain Select
        2. 8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Software Control
      2. 8.4.2 Speaker Amplifier Operating Modes
        1. 8.4.2.1 BTL Mode
        2. 8.4.2.2 PBTL Mode
      3. 8.4.3 Low EMI Modes
        1. 8.4.3.1 Spread Spectrum
        2. 8.4.3.2 Channel to Channel Phase Shift
        3. 8.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 8.4.3.3.2 Phase Synchronization With GPIO
      4. 8.4.4 Thermal Foldback
      5. 8.4.5 Device State Control
      6. 8.4.6 Device Modulation
        1. 8.4.6.1 BD Modulation
        2. 8.4.6.2 1SPW Modulation
        3. 8.4.6.3 Hybrid Modulation
    5. 8.5 Programming and Control
      1. 8.5.1 I2 C Serial Communication Bus
      2. 8.5.2 Hardware Control Mode
      3. 8.5.3 I2 C Target Address
        1. 8.5.3.1 Random Write
        2. 8.5.3.2 Sequential Write
        3. 8.5.3.3 Random Read
        4. 8.5.3.4 Sequential Read
        5. 8.5.3.5 DSP Memory Book, Page and BQ update
        6. 8.5.3.6 Checksum
          1. 8.5.3.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 8.5.3.6.2 Exclusive or (XOR) Checksum
      4. 8.5.4 Control via Software
        1. 8.5.4.1 Startup Procedures
        2. 8.5.4.2 Shutdown Procedures
      5. 8.5.5 Protection and Monitoring
        1. 8.5.5.1 Overcurrent Limit (Cycle-By-Cycle)
        2. 8.5.5.2 Overcurrent Shutdown (OCSD)
        3. 8.5.5.3 DC Detect Error
        4. 8.5.5.4 Overtemperature Shutdown (OTSD)
        5. 8.5.5.5 PVDD Overvoltage and Undervoltage Error
        6. 8.5.5.6 PVDD Drop Detection
        7. 8.5.5.7 Clock Fault
    6. 8.6 Register Maps
      1. 8.6.1 CONTROL PORT Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor Selections
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
      5. 9.2.5 Advanced 2.1 System (Two TAS5828M Devices)
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAD|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 DAD (TSSOP) Package, 32-Pin PadUp, Software Mode, Top View
Table 5-1 Pin Functions - Software Mode
PINTYPE(1)DESCRIPTION
NAMENO.
AGND1GAnalog ground.
AVDD2PInternally regulated 5-V analog supply voltage. This pin must not be used to drive external devices.
GVDD3PGate drive internal regulator output. This pin must not be used to drive external devices.
PDN4DIPower down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
SCL5DII2C serial control clock input.
SDA6DI/OI2C serial control data interface input/output.
SDIN7DIData line to the serial data port.
BCLK8DIBit clock for the digital signal that is active on the input data line of the serial data port.
LRCLK9DIWord select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
GPIO210DI/OGeneral-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x62h). Can be configured to be open drain output or push-pull output.
GPIO111DI/OGeneral-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x61h). Can be configured to be open drain output or push-pull output.
GPIO012DI/OGeneral-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x63h). Can be configured to be open drain output or push-pull output.
ADR13AIA table of resistor value (Pull down to GND) decides the device I2C address. See Table 8-7.
VR_DIG14PInternally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices.
DVDD15P3.3-V or 1.8-V digital power supply.
DGND16GDigital ground.
PVDD17PPVDD voltage input.
18P
31P
32P
PGND21GGround reference for power device circuitry. Connect this pin to system ground.
22G
27G
28G
OUT_A+19OPositive pin for differential speaker amplifier output A.
BST_A+20PConnection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+.
OUT_A-23ONegative pin for differential speaker amplifier output A.
BST_A-24PConnection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-.
BST_B-25PConnection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-.
OUT_B-26ONegative pin for differential speaker amplifier output B.
BST_B+29PConnection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+.
OUT_B+30OPositive pin for differential speaker amplifier output B.
PowerPAD™PGround, connect to grounded heat sink for best system performance.
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)
Figure 5-2 DAD (TSSOP) Package, 32-Pin PadUp, Hardware Mode,Top View
Table 5-2 Pin Functions - Hardware Mode
PINTYPE1DESCRIPTION
NAMENO.
AGND1GAnalog ground.
AVDD2PInternally regulated 5-V analog supply voltage. This pin must not be used to drive external devices.
GVDD3PGate drive internal regulator output. This pin must not be used to drive external devices.
PDN4DIPower down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
HW_SEL05DIAnalog gain and BTL/PBTL mode selection in Hardware Mode . Pull up to DVDD or Pull down to ground with different resistor. See Table 8-6.
HW_SEL16DIPWM Switching Frequency and Spread Spectrum Enable/Disable selection in Hardware Mode. Pull up to DVDD or Pull down to ground with different resistor. See Table 8-5.
SDIN7DIData line to the serial data port.
BCLK8DIBit clock for the digital signal that is active on the input data line of the serial data port.
LRCLK9DIWord select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
MUTE10DISpeaker amplifier Mute. Which must be pulled low (connect to DGND) to MUTE the device and pulled high (connected to DVDD) to exit MUTE state. In Mute state, device output keep in Hi-Z state.
FAULT11DOFault terminal,which is pulled LOW when an internal fault occurs.
PD_DET12DOPVDD Drop detection, which is pulled LOW when the PVDD drop below 8V.
HW_MODE13AIConnect to DVDD directly to ensure device enter into Hardware Control Mode.
VR_DIG14PInternally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices.
DVDD15P3.3-V or 1.8-V digital power supply.
DGND16GDigital ground.
PVDD17PPVDD voltage input.
18P
31P
32P
PGND21GGround reference for power device circuitry. Connect this pin to system ground.
22G
27G
28G
OUT_A+19OPositive pin for differential speaker amplifier output A.
BST_A+20PConnection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+.
OUT_A-23ONegative pin for differential speaker amplifier output A.
BST_A-24PConnection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-.
BST_B-25PConnection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-.
OUT_B-26ONegative pin for differential speaker amplifier output B.
BST_B+29PConnection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+.
OUT_B+30OPositive pin for differential speaker amplifier output B.
PowerPAD™PGround, connect to grounded heat sink for best system performance.
  1. AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)