SCPS193C July   2010  – April 2014 TCA6424A


  1. Features
  2. Description
  3. Revision History
  4. Description (continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 I2C Interface Timing Requirements
    6. 6.6 Reset Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Translation
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 I2C Interface
      3. 8.3.3 Device Address
    4. 8.4 Programming
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Reset Input (RESET)
      3. 8.4.3 Interrupt Output (INT)
      4. 8.4.4 Bus Transactions
        1. Writes
        2. Reads
    5. 8.5 Register Maps
      1. 8.5.1 Control Register and Command Byte
      2. 8.5.2 Register Descriptions
  9. Applications and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Minimizing ICC When I/Os Control LEDs
  10. 10Power Supply Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Operating Power-Supply Voltage Range of 1.65 V to 5.5 V
  • Allows Bidirectional Voltage-Level Translation and GPIO Expansion Between:
    • 1.8-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 2.5-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 3.3-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 5-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
  • I2C to Parallel Port Expander
  • Low Standby Current Consumption of 1 μA
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the SCL and SDA Inputs
    • Vhys = 0.18 V Typ at 1.8 V
    • Vhys = 0.25 V Typ at 2.5 V
    • Vhys = 0.33 V Typ at 3.3 V
    • Vhys = 0.5 V Typ at 5 V
  • 5-V Tolerant I/O Ports
  • Active-Low Reset Input (RESET)
  • Open-Drain Active-Low Interrupt Output (INT)
  • 400-kHz Fast I2C Bus
  • Input/Output Configuration Register
  • Polarity Inversion Register
  • Internal Power-On Reset
  • Power Up With All Channels Configured as Inputs
  • No Glitch On Power Up
  • Noise Filter on SCL/SDA Inputs
  • Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

2 Description

This 24-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)].

The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P-port side and on the SDA/SCL side. This allows the TCA6424A to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs, remain at a 5-V power supply.

Device Information(1)

TCA6424A UQFN (32) 5mm × 5mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.
If used, the exposed center pad must be connected as a secondary ground or left electrically open.

3 Revision History

Changes from B Revision (September 2010) to C Revision

  • Removed hard coded ordering information table. Go
  • Updated document formatting. Go

Changes from A Revision (August 2010) to B Revision

  • Revised document to updated document status from preview to production data.Go
  • Changed document status from "Product Preview to Production Data"Go

Changes from * Revision (July 2010) to A Revision

  • Changed Recommended Supply Sequencing and Rates TableGo

4 Description (continued)

The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage level on the P-port of the TCA6424A is determined by the VCCP.

The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.

The system master can reset the TCA6424A in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The TCA6424A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6424A can remain a simple slave device.

The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus.