Product details


Number of I/Os 24 Features Adjustable I/O level, Configuration registers, Interrupt pin, Reset pin VCC (Min) (V) 1.65 VCC (Max) (V) 5.5 Addresses 2 Rating Catalog Frequency (Max) (kHz) 400 Operating temperature range (C) -40 to 85 open-in-new Find other I2C general-purpose I/Os (GPIOs)

Package | Pins | Size

UQFN (RGJ) 32 25 mm² 5 x 5 open-in-new Find other I2C general-purpose I/Os (GPIOs)


  • Operating Power-Supply Voltage Range of 1.65 V to 5.5 V
  • Allows Bidirectional Voltage-Level Translation and GPIO Expansion Between:
    • 1.8-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 2.5-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 3.3-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 5-V SCL/SDA and
      1.8-V, 2.5-V, 3.3-V, or 5-V P Port
  • I2C to Parallel Port Expander
  • Low Standby Current Consumption of 1 μA
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the SCL and SDA Inputs
    • Vhys = 0.18 V Typ at 1.8 V
    • Vhys = 0.25 V Typ at 2.5 V
    • Vhys = 0.33 V Typ at 3.3 V
    • Vhys = 0.5 V Typ at 5 V
  • 5-V Tolerant I/O Ports
  • Active-Low Reset Input (RESET)
  • Open-Drain Active-Low Interrupt Output (INT)
  • 400-kHz Fast I2C Bus
  • Input/Output Configuration Register
  • Polarity Inversion Register
  • Internal Power-On Reset
  • Power Up With All Channels Configured as Inputs
  • No Glitch On Power Up
  • Noise Filter on SCL/SDA Inputs
  • Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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open-in-new Find other I2C general-purpose I/Os (GPIOs)


This 24-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)].

The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P-port side and on the SDA/SCL side. This allows the TCA6424A to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs, remain at a 5-V power supply.

The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage level on the P-port of the TCA6424A is determined by the VCCP.

The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.

The system master can reset the TCA6424A in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The TCA6424A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6424A can remain a simple slave device.

The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus.

open-in-new Find other I2C general-purpose I/Os (GPIOs)

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet TCA6424A Low-Voltage 24-Bit I2C and SMBus I/O Expander With Interrupt Output, Reset, and Configuration Registers datasheet (Rev. C) Apr. 24, 2014
Application notes I2C Dynamic Addressing Apr. 25, 2019
Application notes Choosing the Correct I2C Device for New Designs Sep. 07, 2016
Selection guides I2C Infographic Flyer Dec. 03, 2015
Application notes Understanding the I2C Bus Jun. 30, 2015
Application notes I2C Bus Pull-Up Resistor Calculation Feb. 13, 2015
User guides I/O Expander EVM User's Guide (Rev. A) Jul. 25, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The IO expander evaluation module (EVM) lets you evaluate TI's portfolio of SMBus and I2C IO expander line devices. The TCA6424A and TCA9539 come installed on the board. The 24-pin TSSOP footprint also supports TCA6408A, TCA6416A, TCA9534, TCA9534ATCA9535, TCA9538, TCA9554, TCA9554A and TCA9555.

  • IO expander evaluation through LEDs or broken out to headers
  • Input evaluation with on board pushbutton switches
  • Example code including necessary functions for each IO expander

Software development

SLVC564A.ZIP (2137 KB)

Design tools & simulation

SCPM027.ZIP (145 KB) - IBIS Model
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide
I2C designer tool
I2C-DESIGNER — Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard with (...)
  • GUI-based web application
  • Exportable designs
  • JSON file uploader
  • Bill of materials generator

Reference designs

12-Gbps Multi-Channel BERT Board Reference Design
TIDA-00426 — This reference design is a 12-Gbps low-cost bit error tester (BERT) capable of generating and checking up to 8 channels of pseudo-random binary sequences (PRBS). This validated design is a convenient way to generate multi-channels high speed serial bit streams of up to 12-Gbps, and checking incoming (...)
document-generic Schematic document-generic User guide
Self-Booting Audio System
TIDA-00609 The purpose of this TI Design is to provide the designer hardware and software tools that can be used as reference for audio systems. The new revision of the PurePath™ Console Motherboard (RevF) adds stand-alone, self-booting capabilities to allow making compelling demos with any EVM that is (...)
document-generic Schematic document-generic User guide
SDI Video Aggregation Reference Design
TIDA-00352 This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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UQFN (RGJ) 32 View options

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