Table 22. Design Parameters

9.2.2.1 Time Measurement

Time measurements in the THS788 device follow the timing of Figure 10. This diagram illustrates that time measurements are valid as long as events do not happen at speeds higher than 200 MHz. If an event happens at less than 5 ns from the previous one, then this event is ignored. The same applies to the SYNC signal. Even though the minimum period is 5 ns, the pulse duration of both Event and SYNC signals can be as low as 200 ps.

Figure 10. Time-Measurement Example at Maximum Retrigger Rate and Minimum Pulse Duration

The TH788 is capable of making time measurements using any combination of rising-falling edge between Event and SYNC. The example in Figure 10 uses rising edges only to trigger the time measurement. Table 23 describes what registers bits must be programmed to achieve the desired combination. Registers to be programmed are 00h, 20h, 40h, and 60h for event channels and 80h for the sync channel. The examples in Figure 11 illustrate the other three combinations. All of the channels can be programmed individually with respect to the sync channel.

Figure 11. Time-Measurement Examples With Different Edge Polarities

9.2.2.2 Output Clock to Data/Strobe Phasing

The output of each channel is an Rdata and Rstrobe signal. The RCLK for all the channels is a common output. Operating at 300 MHz, these signals must be handled carefully. Particularly important are the termination and phase alignment of the signals at the receiving circuitry. Termination has been discussed previously. Phase alignment is now discussed: The two outputs from each channel are clocked out through identical flip-flops with the same internal clock. Data and strobe output edges from a particular channel match well (< 50 pS). The match channel-to-channel is not as good due to the greater wiring distances internal to the TMU. However, the total time difference is below 125 pS. Because the RClock is a common output, the wiring lengths from the four channels must be matched and controlled to achieve good setup and hold times at the input to the receiving circuit. The RClock rising edge is adjusted internal to the TMU to be close to the center of the eye diagram of the data/strobe signals. (The internal clock has a good 50/50 duty cycle. The rising edge clocks out the data/strobe. The falling edge is inverted and used as the RClock after appropriate adjustments for the internal propagation delay times.) The receiving circuitry requirements for setup and hold timing must be carefully examined for the proper timing. Delays may be added to the PCB microstrips to adjust timing. A good rule is 125 ps of delay per inch of microstrip length.

9.2.2.3 Master Clock Input and Clock Multiplier

All of the internal timing of the TMU is derived from the 200-MHz master clock. Therefore, its quality is critical to the accurate operation of the TMU. Absolute accuracy of the master clock linearly affects the accuracy of the measurements. This imposes little burden upon the master clock, as accurate oscillators are easy to procure or distribute. However, the jitter of the master clock is also highly critical to the single-event precision of the TMU and should be absolutely minimized (<3 ps rms). A carefully selected crystal oscillator can meet this requirement. However, jitter can build up quite quickly in a clock distribution scheme and must be carefully controlled. Be careful that the LVDS input to the master clock is not badly distorted or that the rise/fall times are slow (>.6 ns). Discussion of the clock multiplier follows: The TMU operates from a master-clock frequency of 1200 MHz, which implies a measurement period of 0.833 ns. The master counter runs from this frequency, and all the other clocks are divided down from this main clock. An interpolator allows finer precision in time measurement, as discussed elsewhere. The clock multiplier is the circuit that takes the 200-MHz master-clock reference and generates from that the high quality 1200-MHz clock. The clock multiplier consists of five major sections: First is the delay-lock loop (DLL), which is a series connection of 12 identical and closely matched variable time-delay circuits. A single control voltage connects to each of the delay elements. The master 200-MHz clock connects to the input of the DLL. Because the period of 200 MHz is 5 ns, if the control voltage is adjusted to make the time delay of the DLL equal to 5 ns, the input and the output of the delay line is exactly phase matched. A phase detector connected to the input and the output of the delay line can sense this condition accurately, and a feedback loop with a low-offset-error amplifier is included in the clock multiplier to achieve this result. These are the second and third circuit blocks. With 12 equally spaced 200-MHz clock phases, select out six equally spaced 833-ps-wide pulses with AND gates and combine these pulses into a single 1200-MHz clock waveform with a six-input OR gate. The last circuit element is a powerful differential signal buffer to distribute the 1200-MHz clock to the various circuit elements in the TMU. The DLL feedback loop is fairly narrowband, so some time is required to allow the DLL to initialize at start-up (about 100 μs, typical). The DLL is insensitive to the duty cycle of the input 200-MHz clock. Duty cycles of 40/60 to 60/40 are acceptable. What matters most is as little jitter as possible.

9.2.2.4 Temperature Measurement and Alarm Circuit

Chip temperature of the TMU is monitored by a temperature sensor located near the center of the chip. A small buffer outputs a voltage proportional to the absolute temperature of the TMU. The buffer drives a load of up to 100 pF typical (50 pF minimum) and open circuit to 10 kΩ to ground resistive. The output voltage slope is 5 mV, typical. Therefore, the output voltage equation is as follows:

Also included in the TMU is an overtemperature comparator. At approximately 140°C, the alarm goes active, and at approximately 7°C below this temperature, the alarm becomes inactive (hysteresis of 7°C prevents tripping on noise and comparator oscillations). If the alarm goes active, the chip powers down and sets a bit in the serial register.

An alarm output pin is provided that is an open-drain output. Connect this output through a pullup resistor to the 3.3-V power supply. The resistor must be at least 3.3 kΩ. This creates a slow-speed, low-voltage CMOS digital output with a logical 1 being the normal operating state and a logical 0 being the overtemperature state.

9.2.2.5 LVDS-Compatible I/Os

The Event, SYNC, and master-clock inputs are LVDS-compatible input receivers optimized for high-speed and low-time-distortion operation. The Rdata, Rstrobe, and RCLK outputs are similarly LVDS-compatible output drivers optimized for high-speed/low-distortion operation, driving 50-Ω transmission lines. Typically, LVDS data transmission is thought of in terms of 100-Ω twisted-wire-pair (TWP) transmission lines. TWP is not applicable to printed wiring boards and high-speed operation. Therefore, the THS788 device interfaces were designed to operate most effectively with 50-Ω, single-ended transmission lines. Instead of a current-mode output with its correspondingly high output impedance, a more-nearly impedance-matched voltage-mode output driver is used. This minimizes reflections from mismatched transmission line terminations and the resulting waveform distortion. The input receivers do not include the 100-Ω terminating resistor, which must be connected externally to the THS788 device. This was done to accommodate daisy-chaining the THS788 inputs. Input offset voltage was minimized, and the fail-safe feature in the LVDS standard was eliminated in order to minimize distortion.

9.2.2.6 LVDS-Compatible Inputs

The four event inputs, the sync input and the master-clock input all use the same input interface circuitry. Figure 12 is a simplified schematic diagram of the LVDS-compatible receiver input stage. The input signal is impedance-transformed and level-shifted with a PNP emitter-follower and translated into ECL-like differential signals with a common-emitter amplifier. There is no internal termination resistor and no internal pullup/pulldown resistors. Unused inputs may be tied off by connecting both input terminals to ground. If the input terminals are left floating, they are protected by ESD clamps from damage; however, noise may be injected into the THS788 device and may degrade accuracy. The peak input voltage limits are 0.6 V to 1.7 V. Outside of these limiting voltages, parts of the input circuit may saturate and distort the timing.

Figure 12. Simplified Schematic of the LVDS Input

Figure 13 shows the typical input connections. The transmission line lengths must be matched from the driver to the THS788 input [<0.5 inch (1.27 cm) difference] and terminated in a 100-Ω resistor placed close [<0.25 inch (0.635 cm)] to the TMU input pins. The resistor total tolerance should be below 5%. The power dissipation is below 5 mW, so small surface-mounted resistors are preferred.

Figure 13. Typical Input Connection to the THS788

9.2.2.7 LVDS-Compatible Outputs

Figure 14 shows a typical wiring diagram of an LVDS output. The transmission line lengths must be matched. A termination resistor may be required if the chosen receiver does not have an internal resistor. Concerning termination resistors: LVDS was originally conceived with twisted-wire pairs of approximately 100 Ω line-to-line impedance. The 100-Ω resistor between lines is simple and effective to terminate such a line. For the higher-speed operation of the THS788 device, use a pair of 50-Ω transmission lines, such as microstrip on the PC board. The same 100-Ω resistor line-to-line termination works well, because the line signals are equal and opposite in phase. This results in the center of the 100-Ω resistor having a constant voltage equal to the common-mode voltage and each side having an apparent 50-Ω termination. An improvement in the termination can be achieved by splitting the 100 Ω into two 50-Ω resistors and ac-grounding (bypassing) the center to ground with a 1000-pF (not critical) capacitor. The termination improvement is usually small and increases the room and parts count. It is the best approach as long as the PCB layout high-frequency performance is not compromised by the higher parts count. As mentioned previously, the driver is optimized to drive 50-Ω transmission lines and provides a driving-point impedance approximating 50 Ω to suppress reflections. Figure 10 is a simplified schematic of the output driver. A standard ECL-like circuit drives the outputs through 25-Ω resistors. The combination of the resistors and the emitter-follower output impedance approximates 50 Ω. The output emitter-followers are biased by current sources which are switched to conserve power. A feedback loop varies the voltage on the two RLs to set and maintain the 1.28-V common-mode voltage of the LVDS-compatible outputs. Another feedback loop holds the emitters of the current switches to 0.4 V to keep the 4-mA current source from saturation.

The outputs are short-circuit-proof to a 3.3-V power supply. Shorts to ground should be avoided, as the power dissipation in certain components may exceed safe limits.

Figure 14. Typical Output Connection to the THS788

Figure 15. Simplified Schematic of the LVDS Output Driver