SLOS616D March   2010  – March 2015 THS788

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Host Serial Interface DC Characteristics
    7. 7.7 Host Serial Interface AC Characteristics
    8. 7.8 Power Consumption
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Counter, Latches, Clock Multiplier
      2. 8.3.2 Channels, Interpolator
      3. 8.3.3 FIFO
      4. 8.3.4 Calibration, ALU, Tag, Shifter
      5. 8.3.5 Serial Interface, Temperature, Overhead
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial-Results Interface
      2. 8.4.2 Result-Interface Clock
      3. 8.4.3 DDR Mode
      4. 8.4.4 Output Interface Throughput
      5. 8.4.5 Counter Range
        1. 8.4.5.1 Preconditioning Holdoff Delay Time
        2. 8.4.5.2 Arming Conditions
      6. 8.4.6 Resister Map Descriptions for All Channels and Central Register
    5. 8.5 Programming
      1. 8.5.1 Host Processor Bus Interface
        1. 8.5.1.1  Serial Interface
        2. 8.5.1.2  Read vs Write Cycle
        3. 8.5.1.3  Parallel (Broadcast) Write
        4. 8.5.1.4  Address
        5. 8.5.1.5  Data
        6. 8.5.1.6  Reset
        7. 8.5.1.7  Chip ID
        8. 8.5.1.8  Read Operations
        9. 8.5.1.9  Write Operations
        10. 8.5.1.10 Write Operations to Multiple Destinations
      2. 8.5.2 Serial-Results Interface and ALU
        1. 8.5.2.1 Event Latches
        2. 8.5.2.2 FIFO
        3. 8.5.2.3 Result-Interface Operation
        4. 8.5.2.4 Serial Results Latency
        5. 8.5.2.5 TMU Calibration
        6. 8.5.2.6 Temperature Sensor
    6. 8.6 Register Maps
      1. 8.6.1 Register Address Space
      2. 8.6.2 Register Map Detail
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 Time Measurement
        2. 9.2.2.2 Output Clock to Data/Strobe Phasing
        3. 9.2.2.3 Master Clock Input and Clock Multiplier
        4. 9.2.2.4 Temperature Measurement and Alarm Circuit
        5. 9.2.2.5 LVDS-Compatible I/Os
        6. 9.2.2.6 LVDS-Compatible Inputs
        7. 9.2.2.7 LVDS-Compatible Outputs
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)
MIN MAX UNIT
VCC 4 V
Analog I/O to GND(2) –0.3 VCC + 0.3 V
Digital I/O to GND –0.3 VCC + 0.3 V
TJ Maximum junction temperature(1) 150 °C
Tstg Storage temperature 150 °C
(1) The THS788 device has an automatic power shutdown at 140°C, typical.
(2) LVDS outputs are not short-circuit-proof to GND.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3.135 3.465 V
TJ Junction temperature 0 105 °C
MCLOCK frequency 200 MHz

7.4 Thermal Information

THERMAL METRIC(1) THS788 UNIT
PFD (HTQFP)
100 PINS
RθJA Junction-to-ambient thermal resistance 27.2
(60.2 without heat sink)		 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.6
RθJB Junction-to-board thermal resistance 6.8
ψJT Junction-to-top characterization parameter 0.6
ψJB Junction-to-board characterization parameter 6.8
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical conditions are at TJ = 55°C and VCC = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TDC CHARACTERISTICS
Time-measurement precision (LSB) 13.02 ps
Measurement accuracy after calibration, mean –8 8 ps
Single-event accuracy, one sigma 8 ps
Time-measurement temperature coefficient 0.1 ps/°C
Time-measurement voltage coefficient ±30 ps/V
Event input rate 200 MHz
Minimum event pulse duration With preconditioning 2.5 ns
Without preconditioning 250 ps
Minimum event pulse duration 250 ps
Turnon time (ready to take timestamp) 250 μs
MASTER CLOCK CHARACTERISTICS
Frequency 200 MHz
Duty cycle 0.4 0.6
Jitter 3 ps rms
HIGH-SPEED LVDS INPUTS: MCLK, EVENT, SYNC
Differential input voltage 100-Ω termination, line-to-line 200 350 500 mV
Common-mode voltage 1.25 V
Peak voltage, either input 0.6 1.7 V
Input capacitance 1 pF
HIGH-SPEED LVDS OUTPUTS: Rdata, Rstrobe, RCLK
Differential output voltage 100-Ω termination, line-to-line 250 325 400 mV
Common-mode voltage 1.125 1.28 1.375 V
Rise time/fall time 20%/80% 250 ps
Output resistance 40 Ω
TEMPERATURE SENSOR DC CHARACTERISTICS
Output voltage TJ = 65°C 1.69 V
Output voltage temperature slope 5 mV/°C
Max capacitive load 30 pF
Max resistive load 10 kΩ
OVERTEMPERATURE ALARM DC CHARACTERISTICS
Trip point Active-low pulldown 141 °C
Leakage current Temperature < trip point 1 μA
Output voltage, low Isink = 1 ma 0.2 V
OUTPUT INTERFACE TIMING
RCLK duty cycle 45% 50% 55%
Rdata/Rstrobe to RCLK setup time 300 MHz 1.4 ns
150 MHz 3.1
75 MHz 6.4
Rdata/Rstrobe to RCLK hold time 300 MHz 1.5 ns
150 MHz 3.2
75 MHz 6.5
OPERATING PARAMETERS
Coarse counter range 18 34 bit
Coarse counter max time range 14.31 s
Result-interface clock 75 300 MHz
Result-interface transfer format 16 40 bit
Result-interface time range –7.158 7.158 s

7.6 Host Serial Interface DC Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 0.7 × VCC VCC + 0.5 V
VIL Low-level input voltage GND – 0.3 0.3 × VCC V
VOH High-level output voltage VCC – 0.5 VCC + 0.3 V
VOL Low-level output voltage 0 0.4 V
Ilkg Leakage current 1 µA

7.7 Host Serial Interface AC Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HCLK frequency 50 MHz
Rise and fall times 3.5 ns
HCLK duty cycle 40% 50% 60%
Hstrobe high period between two consecutive transactions 40 ns
Hstrobe low to HCLK high setup 5 ns
HCLK high to Hstrobe high hold time 5 ns
Hdata in to HCLK high setup 5 ns
Hdata in to HCLK high hold time 5 ns
HCLK falling edge to Hdata out (L or H) CL = 20 pF 3.25 ns
HCLK falling edge to Hdata out (H or L) CL = 20 pF 3.25 ns

7.8 Power Consumption

Typical conditions are at 55°C junction temperature, VCC = 3.3 V
CONDITION CURRENT UNIT
TYP MAX
One channel plus sync, counter length = 18 bits, output interface speed = 75 MHz 420 mA
As above with an additional channel add 125 mA
Output interface speed 150 MHz add 10 mA
300 MHz add 25
Counter length 27 bits add 60 mA
34 bits add 105
Four-channel current 18 bits 75 MHz 795 1075 mA
150 MHz 805 1090
300 MHz 820 1101
27 bits 75 MHz 855 1150
150 MHz 865 1165
300 MHz 880 1176
34 bits 75 MHz 900 1210
150 MHz 910 1225
300 MHz 925 1236

7.9 Typical Characteristics

THS788 sigma_vs_window_los616.gif
Figure 1. Typical Per Channel Sigmas vs 5-ns (200-MHz) Window
THS788 D001_SLOS776_SLOS897.gif
Figure 2. Four-Channel Supply Current vs Rdata, Counter, and Rclock Functional Modes