SCPS260C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7 Programming Guidelines

When configuring the TIC12400-Q1, it is critical to follow the programming guideline summarized below (see Table 8-59) to ensure proper behavior of the device:

Table 8-59 TIC12400-Q1 Programming Guidelines
CategoryProgramming requirement
Threshold setup:
  • Continuous mode
  • Regular polling mode
  • Matrix mode (non-matrix inputs)
  • THRES2B ≥ THRES2A (for IN12 to IN17)
  • THRES3C ≥ THRES3B ≥ THRES3A (for IN18 to IN22)
  • THRES9 ≥ THRES8 ≥ THRES3C ≥ THRES3B ≥ THRES3A (for IN23)
Threshold setup:
  • VS measurement
  • VS0_THRES2B ≥ VS0_THRES2A
  • VS1_THRES2B ≥ VS1_THRES2A
4×4 Matrix mode (MATRIX [4:3] = 2'b01)
  • POLL_EN=1
  • IN_EN[7:4]=4’b1111; IN_EN[13:10]= 4’b1111
  • MODE[7:4] = 4’b0000; MODE[13:10] = 4’b0000
  • CS_SELECT[7:4]= 4’b1111; CS_SELECT[13:10]= 4’b0000
  • IWETT(CSI) > IWETT (CSO):
    1. WC_CFG0[20:18] < WC_CFG0[8:6]
    2. WC_CFG0[23:21] < WC_CFG0[11:9]
    3. WC_CFG1[2:0] > WC_CFG0[14:12]
  • If TW event is expected, CSO can only be set to 1 mA or 2 mA:
    1. If WC_CFG0[8:6]= 3’b001: WC_CFG0[20:18]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG0[8:6]= 3’b010: WC_CFG0[20:18] = 3’b011
    2. If WC_CFG0[11:9]= 3’b001: WC_CFG0[23:21]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG0[11:9]= 3’b010: WC_CFG0[23:21] = 3’b011
    3. If WC_CFG1[2:0]= 3’b001: WC_CFG0[14:12]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG1[2:0]= 3’b010: WC_CFG0[14:12] = 3’b011
5×5 Matrix mode (MATRIX [4:3] = 2'b10)
  • POLL_EN=1
  • IN_EN[8:4]= 5’b11111; IN_EN[14:10]= 5’b11111
  • MODE[8:4] = 5’b00000; MODE[14:10] = 5’b00000
  • CS_SELECT[8:4]= 5’b11111; CS_SELECT[14:10]= 5’b00000
  • IWETT(CSI) > IWETT (CSO):
    1. WC_CFG0[20:18] <WC_CFG0[8:6]
    2. WC_CFG0[23:21] < WC_CFG0[11:9]
    3. WC_CFG1[2:0] > WC_CFG0[14:12]
    4. WC_CFG1[5:3] > WC_CFG0[17:15]
  • If TW event is expected, CSO can only be set to 1 mA or 2 mA:
    1. If WC_CFG0[8:6]= 3’b001: WC_CFG0[20:18]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG0[8:6]= 3’b010: WC_CFG0[20:18] = 3’b011
    2. If WC_CFG0[11:9]= 3’b001: WC_CFG0[23:21]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG0[11:9]= 3’b010: WC_CFG0[23:21] = 3’b011
    3. If WC_CFG1[2:0]= 3’b001: WC_CFG0[14:12]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG1[2:0]= 3’b010: WC_CFG0[14:12] = 3’b011
    4. If WC_CFG1[5:3]= 3’b001: WC_CFG0[17:15]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG1[5:3]= 3’b010:WC_CFG0[17:15] = 3’b011
6×6 Matrix mode (MATRIX [4:3]= 2’b11)
  • POLL_EN=1
  • IN_EN[9:4]= 6’b111111; IN_EN[15:10]= 6’b111111
  • MODE[9:4] = 6’b000000; MODE[15:10] = 6’b000000
  • CS_SELECT[9:4]= 6’b111111; CS_SELECT[15:10]= 6’b000000
  • IWETT(CSI) > IWETT (CSO):
    1. WC_CFG0[20:18] <WC_CFG0[8:6]
    2. WC_CFG0[23:21] < WC_CFG0[11:9]
    3. WC_CFG1[2:0] > WC_CFG0[14:12]
    4. WC_CFG1[5:3] > WC_CFG0[17:15]
  • If TW event is expected, CSO can only be set to 1 mA or 2 mA:
    1. If WC_CFG0[8:6]= 3’b001: WC_CFG0[20:18]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG0[8:6]= 3’b010: WC_CFG0[20:18] = 3’b011
    2. If WC_CFG0[11:9]= 3’b001: WC_CFG0[23:21]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG0[11:9]= 3’b010: WC_CFG0[23:21] = 3’b011
    3. If WC_CFG1[2:0]= 3’b001: WC_CFG0[14:12]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG1[2:0]= 3’b010: WC_CFG0[14:12] = 3’b011
    4. If WC_CFG1[5:3]= 3’b001: WC_CFG0[17:15]= 3’b010, 3’b011, 3’b100, 3’b101, 3’b110, or 3’b111; If WC_CFG1[5:3]= 3’b010: WC_CFG0[17:15] = 3’b011
Clean Current Polling (if CCP_INx= 1 in the CCP_CFG1 register)At least one input (standard or matrix) or the VS measurement has to be enabled: IN_EN_x= 1 in the IN_EN register or CONFIG [16]= 1’b1(1)
Wetting current auto-scaling (if WC_CFG1 [22:21] != 2b’11)
  • The wetting current auto-scaling feature is only activated in the continuous mode: POLL_EN= 0 (2)
  • The wetting current auto-scaling only applies to 10 mA or 15 mA wetting currents: WC_INx bits = 3’b100, 3’b101, 3’b110, or 3’b111 in the WC_CFG0 and WC_CFG1 registers.(2)
Wetting current diagnostic (If CONFIG [21:18] != 4b’0000)
  • At least one channel has to be enabled from IN0 to IN3 (IN_EN[3:0] != 4b’0000)
  • Inputs IN0 to IN3 need to be configured to ADC input mode: MODE[3:0] = 4’b1111
  • Inputs IN0 and IN1 need to be configured to CSO: CS SELECT [1:0]= 2b’00
  • Inputs IN2 and IN3 need to be configured to CSI: CS SELECT [3:2]= 2b’11
  • Continuous mode
  • Standard polling mode
tPOLL_TIME and tPOLL_ACT_TIME settings have to meet the below requirement: tPOLL_TIME ≥ 1.3 ×[ tPOLL_ACT_TIME + n × 24 μs + 10 μs](3)(4)
  • n: the number of enabled channels configured in register IN_EN
  • tPOLL_TIME: timing setting configured in CONFIG[4:1]
  • tPOLL_ACT_TIME: timing setting configured in CONFIG[8:5]
Matrix polling modetPOLL_TIME ,tPOLL_ACT_TIME, and tPOLL_ACT_TIME_M settings have to meet the below requirement: tPOLL_TIME > 1.3 × [ m × tPOLL_ACT_TIME_M + tPOLL_ACT_TIME + n × 24 μs + 10 μs] (3)(4)
  • n: the number of enabled channels configured in register IN_EN
  • m: 16 for 4×4 matrix; 25 for 5×5 matrix; 36 for 6×6 matrix
  • tPOLL_TIME: timing setting configured in CONFIG[4:1]
  • tPOLL_ACT_TIME_M: timing setting configured in MATRIX[2:0]
  • tPOLL_ACT_TIME: timing setting configured in CONFIG[8:5]
(1) This is a soft requirement to take advantage of the clean current polling feature. The feature takes no effect otherwise.
(2) These are soft requirements to take advantage of the wetting current auto-scaling feature. The feature takes no effect otherwise.
(3) If WCD is enabled, add additional 96 μs
(4) If CCP is enabled, add tCCP_TRAN +tCCP_TIME, where tCCP_TIME is the timing setting configured in CCP_CFG0[6:4]