SCPS260C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Register Maps

Table 8-11 lists the memory-mapped registers for the TIC12400-Q1. All register offset addresses not listed in Table 8-11 should be considered as reserved locations and the register contents should not be modified.

Table 8-11 TIC12400-Q1 Registers
OFFSETTYPERESETACRONYMREGISTER NAMESECTION
1hR20hDEVICE_IDDevice ID RegisterGo
2hRC1hINT_STATInterrupt Status RegisterGo
3hRFFFFhCRCCRC Result RegisterGo
4hR0hIN_STAT_MISCMiscellaneous Status RegisterGo
5hR0hIN_STAT_COMPComparator Status RegisterGo
6h-7hR0hIN_STAT_ADC0, IN_STAT_ADC1ADC Status RegisterGo
8h-9hR0hIN_STAT_MATRIX0, IN_STAT_MATRIX1Matrix Status RegisterGo
Ah-16hR0hANA_STAT0- ANA_STAT12ADC Raw Code RegisterGo
17h-19hRESERVEDRESERVED
1AhR/W0hCONFIGDevice Global Configuration RegisterGo
1BhR/W0hIN_ENInput Enable RegisterGo
1ChR/W0hCS_SELECTCurrent Source/Sink Selection RegisterGo
1Dh-1EhR/W0hWC_CFG0, WC_CFG1Wetting Current Configuration RegisterGo
1Fh-20hR/W0hCCP_CFG0, CCP_CFG1Clean Current Polling RegisterGo
21hR/W0hTHRES_COMPComparator Threshold Control RegisterGo
22h-23hR/W0hINT_EN_COMP1, INT_EN_COMP2Comparator Input Interrupt Generation Control RegisterGo
24hR/W0hINT_EN_CFG0Global Interrupt Generation Control RegisterGo
25h-28hR/W0hINT_EN_CFG1- INT_EN_CFG4ADC Input Interrupt Generation Control RegisterGo
29h-2DhR/W0hTHRES_CFG0- THRES_CFG4ADC Threshold Control RegisterGo
2Eh- 30hR/W0hTHRESMAP_CFG0- THRESMAP_CFG2ADC Threshold Mapping RegisterGo
31hR/W0hMatrixMatrix Setting RegisterGo
32hR/W0hModeMode Setting RegisterGo

8.6.1 DEVICE_ID Register (Offset = 1h) [Reset = 20h]

DEVICE_ID is shown in Figure 8-24 and described in Table 8-12.

Return to Summary Table.

This register represents the device ID of the TIC12400-Q1.

Figure 8-24 DEVICE_ID Register
232221201918171615141312
RESERVED
R-0h
11109876543210
RESERVEDMAJORMINOR
R-0hR-2hR-0h
LEGEND: R = Read only
Table 8-12 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
23-11RESERVEDR0h

RESERVED

10-4MAJORR2h

These 7 bits represents major revision ID. For TIC12400-Q1 the major revision ID is 2h.

3-0MINORR0h

These 4 bits represents minor revision ID. For TIC12400-Q1 the minor revision ID is 0h

8.6.2 INT_STAT Register (Offset = 2h) [reset = 1h]

INT_STAT is shown in Figure 8-25 and described in Table 8-13.

Return to Summary Table.

This register records the information of the event as it occurs in the device. A READ command executed on this register clears its content and resets the register to its default value. The INT pin is released at the rising edge of the CS pin from the READ command.

Figure 8-25 INT_STAT Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCHK_FAILADC_DIAGWET_DIAGVS1VS0CRC_CALC
R-0hRC-0hRC-0hRC-0hRC-0hRC-0hRC-0h
76543210
UVOVTWTSDSSCPRTY_FAILSPI_FAILPOR
RC-0hRC-0hRC-0hRC-0hRC-0hRC-0hRC-0hRC-1h
LEGEND: R = Read only; RC = Read to clear
Table 8-13 INT_STAT Register Field Descriptions
BitFieldTypeResetDescription
23-14RESERVEDR0h

RESERVED

13CHK_FAILRC0h

0h = Default factory setting is successfully loaded upon device initialization or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = An error is detected when loading factory settings into the device upon device initialization.

During device initialization, factory settings are programmed into the device to allow proper device operation. The device performs a self-check after the device is programmed to diagnose whether correct settings are loaded. If the self-check returns an error, the CHK_FAIL bit is flagged to logic 1 along with the POR bit. The host controller is then recommended to initiate a software reset (see section Software Reset) to re-initialize the device and allow correct settings to be re-programmed.

12ADC_DIAGRC0h

0h = No ADC self-diagnostic error is detected or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = ADC self-diagnostic error is detected.

The ADC Self-Diagnostic feature (see section ADC Self-Diagnostic) can be activated to monitor the integrity of the internal ADC. The ADC_DIAG bit is flagged to logic 1 if an ADC error is diagnosed.

11WET_DIAGRC0h

0h = No wetting current error is detected, or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Wetting current error is detected.

The Wetting Current Diagnostic feature (see section Wetting Current Diagnostic) can be activated to monitor the integrity of the internal current sources or sinks. The WET_DIAG bit is flagged to logic 1 if a wetting current error is diagnosed.

10VS1RC0h

0h = No VS voltage state change occurred with respect to VS1_THRES2A or VS1_THRES2B or the status got cleared after a READ command was executed on the INT_STAT register.

1h = VS voltage state change occurred with respect to VS1_THRES2A or VS1_THRES2B.

The VS1 interrupt bit indicates whether VS voltage state change occurred with respect to thresholds VS1_THRES2A and VS1_THRES2B if the VS Measurement feature (see section VS Measurement) is activated.

9VS0RC0h

0h = No VS voltage state change occurred with respect to VS0_THRES2A or VS0_THRES2B or the status got cleared after a READ command was executed on the INT_STAT register.

1h = VS voltage state change occurred with respect to VS0_THRES2A or VS0_THRES2B.

The VS0 interrupt bit indicates whether VS voltage state change occurred with respect to thresholds VS0_THRES2A and VS0_THRES2B if the VS Measurement feature (see section VS Measurement) is activated.

8CRC_CALCRC0h

0h = CRC calculation is running, not started, or was acknowledged after a READ command was executed on the INT_STAT register.

1h = CRC calculation is finished.

CRC calculation (see section Cyclic Redundancy Check (CRC)) can be triggered to make sure correct register values are programmed into the device. Once the calculation is completed, the CRC_CALC bit is flagged to logic 1 to indicate completion of the calculation, and the result can then be accessed from the CRC (offset = 3h) register.

7UVRC0h

0h = No under-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Under-voltage condition occurred or cleared on the VS pin.

When the UV bit is flagged to logic 1, it indicates the Under-Voltage (UV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the UV operation, please refer to section VS under-voltage (UV) condition.

6OVRC0h

0h = No over-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Over-voltage condition occurred or cleared on the VS pin.

When the OV bit is flagged to logic 1, it indicates the Over-Voltage (OV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the OV operation, please refer to section VS over-voltage (OV) condition.

5TWRC0h

0h = No temperature warning event occurred or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Temperature warning event occurred or cleared.

When the TW bit is flagged to logic 1, it indicates the temperature warning event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature warning operation, please refer to section Temperature Warning (TW)

4TSDRC0h

0h = No temperature Shutdown event occurred or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Temperature Shutdown event occurred or cleared.

When the TSD bit is flagged to logic 1, it indicates the temperature shutdown event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature shutdown operation, please refer to section Temperature shutdown (TSD)

3SSCRC0h

0h = No switch state change occurred or the status got cleared after a READ command was executed on the INT_STAT register.

1h = Switch state change occurred.

The Switch State Change (SSC) bit indicates whether input threshold crossing has occurred from switch inputs IN0 to IN23. This bit is also flagged to logic 1 after the first polling cycle is completed after device polling is triggered.

2PRTY_FAILRC0h

0h = No parity error occurred in the last received SI stream or the error status got cleared after a READ command was executed on the INT_STAT register.

1h = Parity error occurred.

When the PRTY_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The value of this register bit is mirrored to the PRTY_FLAG SPI status flag.

1SPI_FAILRC0h

0h = 32 clock pulse during a CS = low sequence was detected or the error status got cleared after a READ command was executed on the INT_STAT register.

1h = SPI error occurred

When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit is flagged to logic 1, and the data received is considered invalid. The value of this register bit is mirrored to the SPI_FLAG SPI status flag. Note the SPI_FAIL bit is not flagged if SCLK is not present.

0PORRC1h

0h = no Power-On-Reset (POR) event occurred or the status got cleared after a READ command was executed on the INT_STAT register.

1h = Power-On-Reset (POR) event occurred.

The Power-On-Reset (POR) interrupt bit indicates whether a reset event has occurred. A reset event sets the registers to their default values and re-initializes the device state machine. This bit is asserted after a successful power-on-reset, hardware reset, or software reset. The value of this register bit is mirrored to the POR SPI status flag.

8.6.3 CRC Register (Offset = 3h) [Reset = FFFFh]

CRC is shown in Figure 8-26 and described in Table 8-14.

Return to Summary Table.

This register returns the CRC-16-CCCIT calculation result. The microcontroller can compare this value with its own calculated value to ensure correct register settings are programmed to the device.

Figure 8-26 CRC Register
23222120191817161514131211109876543210
RESERVEDCRC
R-0hR-FFFFh
LEGEND: R = Read only
Table 8-14 CRC Register Field Descriptions
BitFieldTypeResetDescription
23-16RESERVEDR0h

Reserved

15-0CRCRFFFFh

CRC-16-CCITT calculation result: Bit1: LSB of CRC Bit16: MSB or CRC

8.6.4 IN_STAT_MISC Register (Offset = 4h) [Reset = 0h]

IN_STAT_MISC is shown in Figure 8-27 and described in Table 8-15.

Return to Summary Table.

This register indicates current device status unrelated to switch input monitoring.

Figure 8-27 IN_STAT_MISC Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDADC_DIN3_DIN2_DIN1_DIN0_D
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
VS1_STATVS0_STATUV_STATOV_STATTW_STATTSD_STAT
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-15 IN_STAT_MISC Register Field Descriptions
BitFieldTypeResetDescription
23-13RESERVEDR0h

Reserved

12ADC_DR0h

0h = No error is identified from ADC self-diagnostic.

1h = An error is identified from ADC self-diagnostic.

11IN3_DR0h

0h = Current sink on IN3 is operational.

1h = Current sink on IN3 is abnormal.

10IN2_DR0h

0h = Current sink on IN2 is operational.

1h = Current sink on IN2 is abnormal.

9IN1_DR0h

0h = Current source on IN1 is operational.

1h = Current source on IN1 is abnormal.

8IN0_DR0h

0h = Current source on IN0 is operational.

1h = Current source on IN0 is abnormal.

7-6VS1_STATR0h

0h = VS voltage is below threshold VS1_THRES2A.

1h = VS voltage is below threshold VS1_THRES2B and equal to or above threshold VS1_THRES2A.

2h = VS voltage is equal to or above threshold VS1_THRES2B.

3h = N/A.

5-4VS0_STATR0h

0h = VS voltage is below threshold VS0_THRES2A.

1h = VS voltage is below threshold VS0_THRES2B and equal to or above threshold VS0_THRES2A.

2h = VS voltage is equal to or above threshold VS0_THRES2B.

3h = N/A

3UV_STATR0h

0h = VS voltage is above the under-voltage condition threshold.

1h = VS voltage is below the under-voltage condition threshold.

2OV_STATR0h

0h = VS voltage is below the over-voltage condition threshold.

1h = VS voltage is above the over-voltage condition threshold.

1TW_STATR0h

0h = Device junction temperature is below the temperature warning threshold TTW.

1h = Device junction temperature is above the temperature warning threshold TTW.

0TSD_STATR0h

0h = Device junction temperature is below the temperature shutdown threshold TTSD.

1h = Device junction temperature is above the temperature shutdown threshold TTSD.

8.6.5 IN_STAT_COMP Register (Offset = 5h) [Reset = 0h]

IN_STAT_COMP is shown in Figure 8-28 and described in Table 8-16.

Return to Summary Table.

This register indicates whether an input is below or above the comparator threshold when it is configured as comparator input mode.

Figure 8-28 IN_STAT_COMP Register
2322212019181716
INC_23INC_22INC_21INC_20INC_19INC_18INC_17INC_16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
INC_15INC_14INC_13INC_12INC_11INC_10INC_9INC_8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INC_7INC_6INC_5INC_4INC_3INC_2INC_1INC_0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only
Table 8-16 IN_STAT_COMP Register Field Descriptions
BitFieldTypeResetDescription
23INC_23R0h

0h = Input IN23 is below the comparator threshold.

1h = Input IN23 is above the comparator threshold.

22INC_22R0h

0h = Input IN22 is below the comparator threshold.

1h = Input IN22 is above the comparator threshold.

21INC_21R0h

0h = Input IN21 is below the comparator threshold.

1h = Input IN21 is above the comparator threshold.

20INC_20R0h

0h = Input IN20 is below the comparator threshold.

1h = Input IN20 is above the comparator threshold.

19INC_19R0h

0h = Input IN19 is below the comparator threshold

1h = Input IN19 is above the comparator threshold

18INC_18R0h

0h = Input IN18 is below the comparator threshold

1h = Input IN18 is above the comparator threshold

17INC_17R0h

0h = Input IN17 is below the comparator threshold

1h = Input IN17 is above the comparator threshold

16INC_16R0h

0h = Input IN16 is below the comparator threshold

1h = Input IN16 is above the comparator threshold

15INC_15R0h

0h = Input IN15 is below the comparator threshold

1h = Input IN15 is above the comparator threshold

14INC_14R0h

0h = Input IN14 is below the comparator threshold

1h = Input IN14 is above the comparator threshold

13INC_13R0h

0h = Input IN13 is below the comparator threshold

1h = Input IN13 is above the comparator threshold

12INC_12R0h

0h = Input IN12 is below the comparator threshold

1h = Input IN12 is above the comparator threshold

11INC_11R0h

0h = Input IN11 is below the comparator threshold

1h = Input IN11 is above the comparator threshold

10INC_10R0h

0h = Input IN10 is below the comparator threshold

1h = Input IN10 is above the comparator threshold

9INC_9R0h

0h = Input IN9 is below the comparator threshold

1h = Input IN9 is above the comparator threshold

8INC_8R0h

0h = Input IN8 is below the comparator threshold

1h = Input IN8 is above the comparator threshold

7INC_7R0h

0h = Input IN7 is below the comparator threshold

1h = Input IN7 is above the comparator threshold

6INC_6R0h

0h = Input IN6 is below the comparator threshold

1h = Input IN6 is above the comparator threshold

5INC_5R0h

0h = Input IN5 is below the comparator threshold

1h = Input IN5 is above the comparator threshold

4INC_4R0h

0h = Input IN4 is below the comparator threshold

1h = Input IN4 is above the comparator threshold

3INC_3R0h

0h = Input IN3 is below the comparator threshold

1h = Input IN3 is above the comparator threshold

2INC_2R0h

0h = Input IN2 is below the comparator threshold

1h = Input IN2 is above the comparator threshold

1INC_1R0h

0h = Input IN1 is below the comparator threshold

1h = Input IN1 is above the comparator threshold

0INC_0R0h

0h = Input IN0 is below the comparator threshold

1h = Input IN0 is above the comparator threshold

8.6.6 IN_STAT_ADC0 Register (Offset = 6h) [Reset = 0h]

IN_STAT_ADC0 is shown in Figure 8-29 and described in Table 8-17.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold (for IN0-IN11) when it is configured as ADC input mode. For IN12-IN17, there are 2 thresholds and the register bits indicate whether the input is below, above or in-between the 2 thresholds.

Figure 8-29 IN_STAT_ADC0 Register
2322212019181716
INA_17INA_16INA_15INA_14
R-0hR-0hR-0hR-0h
15141312111098
INA_13INA_12INA_11INA_10INA_9INA_8
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
INA_7INA_6INA_5INA_4INA_3INA_2INA_1INA_0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only
Table 8-17 IN_STAT_ADC0 Register Field Descriptions
BitFieldTypeResetDescription
23-22INA_17R0h

0h = Input IN17 is below threshold 2A

1h = Input IN17 is below threshold 2B and equal to or above threshold 2A

2h = Input IN17 is equal to or above threshold 2B

3h = N/A

21-20INA_16R0h

0h = Input IN16 is below threshold 2A

1h = Input IN16 is below threshold 2B and equal to or above threshold 2A

2h = Input IN16 is equal to or above threshold 2B

3h = N/A

19-18INA_15R0h

0h = Input IN15 is below threshold 2A

1h = Input IN15 is below threshold 2B and equal to or above threshold 2A

2h = Input IN15 is equal to or above threshold 2B

3h = N/A

17-16INA_14R0h

0h = Input IN14 is below threshold 2A

1h = Input IN14 is below threshold 2B and equal to or above threshold 2A

2h = Input IN14 is equal to or above threshold 2B

3h = N/A

15-14INA_13R0h

0h = Input IN13 is below threshold 2A

1h = Input IN13 is below threshold 2B and equal to or above threshold 2A

2h = Input IN13 is equal to or above threshold 2B

3h = N/A

13-12INA_12R0h

0h = Input IN12 is below threshold 2A

1h = Input IN12 is below threshold 2B and equal to or above threshold 2A

2h = Input IN12 is equal to or above threshold 2B

3h = N/A

11INA_11R0h

0h = Input IN11 is below configured threshold

1h = Input IN11 is above configured threshold

10INA_10R0h

0h = Input IN10 is below configured threshold

1h = Input IN10 is above configured threshold

9INA_9R0h

0h = Input IN9 is below configured threshold

1h = Input IN9 is above configured threshold

8INA_8R0h

0h = Input IN8 is below configured threshold

1h = Input IN8 is above configured threshold

7INA_7R0h

0h = Input IN7 is below configured threshold

1h = Input IN7 is above configured threshold

6INA_6R0h

0h = Input IN6 is below configured threshold

1h = Input IN6 is above configured threshold

5INA_5R0h

0h = Input IN5 is below configured threshold

1h = Input IN5 is above configured threshold

4INA_4R0h

0h = Input IN4 is below configured threshold

1h = Input IN4 is above configured threshold

3INA_3R0h

0h = Input IN3 is below configured threshold

1h = Input IN3 is above configured threshold

2INA_2R0h

0h = Input IN2 is below configured threshold

1h = Input IN2 is above configured threshold

1INA_1R0h

0h = Input IN1 is below configured threshold

1h = Input IN1 is above configured threshold

0INA_0R0h

0h = Input IN0 is below configured threshold

1h = Input IN0 is above configured threshold

8.6.7 IN_STAT_ADC1 Register (Offset = 7h) [Reset = 0h]

IN_STAT_ADC1 is shown in Figure 8-30 and described in Table 8-18.

Return to Summary Table.

This register indicates whether an input is above or below the programmed thresholds 3A, 3B, and 3C when it is configured as ADC input mode. For IN23, there are 5 thresholds that can be programmed.

Figure 8-30 IN_STAT_ADC1 Register
232221201918171615141312
RESERVEDINA_23
R-0hR-0h
11109876543210
INA_23INA_22INA_21INA_20INA_19INA_18
R-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only
Table 8-18 IN_STAT_ADC1 Register Field Descriptions
BitFieldTypeResetDescription
23-13RESERVEDR0h

Reserved

12-10INA_23R0h

0h = Input IN23 is below threshold 3A

1h = Input IN23 is below threshold 3B and equal to or above threshold 3A

2h = Input IN23 is below threshold 3C and equal to or above threshold 3B

3h = Input IN23 is below threshold THRES8 and equal to or above threshold 3C

4h = Input IN23 is below threshold THRES9 and equal to or above threshold THRES8

5h = Input IN23 is equal to or above threshold THRES9

9-8INA_22R0h

0h = Input IN22 is below threshold 3A

1h = Input IN22 is below threshold 3B and equal to or above threshold 3A

2h = Input IN22 is below threshold 3C and equal to or above threshold 3B

3h = Input IN22 is equal to or above threshold 3C

7-6INA_21R0h

0h = Input IN21 is below threshold 3A

1h = Input IN21 is below threshold 3B and equal to or above threshold 3A

2h = Input IN21 is below threshold 3C and equal to or above threshold 3B

3h = Input IN21 is equal to or above threshold 3C

5-4INA_20R0h

0h = Input IN20 is below threshold 3A

1h = Input IN20 is below threshold 3B and equal to or above threshold 3A

2h = Input IN20 is below threshold 3C and equal to or above threshold 3B

3h = Input IN20 is equal to or above threshold 3C

3-2INA_19R0h

0h = Input IN19 is below threshold 3A

1h = Input IN19 is below threshold 3B and equal to or above threshold 3A

2h = Input IN19 is below threshold 3C and equal to or above threshold 3B

3h = Input IN19 is equal to or above threshold 3C

1-0INA_18R0h

0h = Input is IN18 is below threshold 3A

1h = Input is IN18 is below threshold 3B and equal to or above threshold 3A

2h = Input is IN18 is below threshold 3C and equal to or above threshold 3B

3h = Input is IN18 is equal to or above threshold 3C

8.6.8 IN_STAT_MATRIX0 Register (Offset = 8h) [Reset = 0h]

IN_STAT_MATRIX0 is shown in Figure 8-31 and described in Table 8-19.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to IN10-IN13.

Figure 8-31 IN_STAT_MATRIX0 Register
2322212019181716
INMAT_13_IN9INMAT_13_IN8INMAT_13_IN7INMAT_13_IN6INMAT_13_IN5INMAT_13_IN4INMAT_12_IN9INMAT_12_IN8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
INMAT_12_IN7INMAT_12_IN6INMAT_12_IN5INMAT_12_IN4INMAT_11_IN9INMAT_11_IN8INMAT_11_IN7INMAT_11_IN6
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INMAT_11_IN5INMAT_11_IN4INMAT_10_IN9INMAT_10_IN8INMAT_10_IN7INMAT_10_IN6INMAT_10_IN5INMAT_10_IN4
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only
Table 8-19 IN_STAT_MATRIX0 Register Field Descriptions
BitFieldTypeResetDescription
23INMAT_13_IN9R0h

0h = Input IN13 is below threshold while IN9 pulled to GND

1h = Input IN13 is above threshold while IN9 pulled to GND

22INMAT_13_IN8R0h

0h = Input IN13 is below threshold while IN8 pulled to GND

1h = Input IN13 is above threshold while IN8 pulled to GND

21INMAT_13_IN7R0h

0h = Input IN13 is below threshold while IN7 pulled to GND

1h = Input IN13 is above threshold while IN7 pulled to GND

20INMAT_13_IN6R0h

0h = Input IN13 is below threshold while IN6 pulled to GND

1h = Input IN13 is above threshold while IN6 pulled to GND

19INMAT_13_IN5R0h

0h = Input IN13 is below threshold while IN5 pulled to GND

1h = Input IN13 is above threshold while IN5 pulled to GND

18INMAT_13_IN4R0h

0h = Input IN13 is below threshold while IN4 pulled to GND

1h = Input IN13 is above threshold while IN4 pulled to GND

17INMAT_12_IN9R0h

0h = Input IN12 is below threshold while IN9 pulled to GND

1h = Input IN12 is above threshold while IN9 pulled to GND

16INMAT_12_IN8R0h

0h = Input IN12 is below threshold while IN8 pulled to GND.

1h = Input IN12 is above threshold while IN8 pulled to GND.

15INMAT_12_IN7R0h

0h = Input IN12 is below threshold while IN7 pulled to GND.

1h = Input IN12 is above threshold while IN7 pulled to GND.

14INMAT_12_IN6R0h

0h = Input IN12 is below threshold while IN6 pulled to GND.

1h = Input IN12 is above threshold while IN6 pulled to GND.

13INMAT_12_IN5R0h

0h = Input IN12 is below threshold while IN5 pulled to GND.

1h = Input IN12 is above threshold while IN5 pulled to GND.

12INMAT_12_IN4R0h

0h = Input IN12 is below threshold while IN4 pulled to GND.

1h = Input IN12 is above threshold while IN4 pulled to GND.

11INMAT_11_IN9R0h

0h = Input IN11 is below threshold while IN9 pulled to GND.

1h = Input IN11 is above threshold while IN9 pulled to GND.

10INMAT_11_IN8R0h

0h = Input IN11 is below threshold while IN8 pulled to GND.

1h = Input IN11 is above threshold while IN8 pulled to GND.

9INMAT_11_IN7R0h

0h = Input IN11 is below threshold while IN7 pulled to GND.

1h = Input IN11 is above threshold while IN7 pulled to GND.

8INMAT_11_IN6R0h

0h = Input IN11 is below threshold while IN6 pulled to GND.

1h = Input IN11 is above threshold while IN6 pulled to GND.

7INMAT_11_IN5R0h

0h = Input IN11 is below threshold while IN5 pulled to GND.

1h = Input IN11 is above threshold while IN5 pulled to GND.

6INMAT_11_IN4R0h

0h = Input IN11 is below threshold while IN4 pulled to GND.

1h = Input IN11 is above threshold while IN4 pulled to GND.

5INMAT_10_IN9R0h

0h = Input IN10 is below threshold while IN9 pulled to GND.

1h = Input IN10 is above threshold while IN9 pulled to GND.

4INMAT_10_IN8R0h

0h = Input IN10 is below threshold while IN8 pulled to GND.

1h = Input IN10 is above threshold while IN8 pulled to GND.

3INMAT_10_IN7R0h

0h = Input IN10 is below threshold while IN7 pulled to GND.

1h = Input IN10 is above threshold while IN7 pulled to GND.

2INMAT_10_IN6R0h

0h = Input IN10 is below threshold while IN6 pulled to GND.

1h = Input IN10 is above threshold while IN6 pulled to GND.

1INMAT_10_IN5R0h

0h = Input IN10 is below threshold while IN5 pulled to GND.

1h = Input IN10 is above threshold while IN5 pulled to GND.

0INMAT_10_IN4R0h

0h = Input IN10 is below threshold while IN4 pulled to GND.

1h = Input IN10 is above threshold while IN4 pulled to GND.

8.6.9 IN_STAT_MATRIX1 Register (Offset = 9h) [Reset = 0h]

IN_STAT_MATRIX1 is shown in Figure 8-32 and described in Table 8-20.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to IN14-IN15. This register also indicates the status of IN0-IN11 with respect to the common threshold THRES_COM.

Figure 8-32 IN_STAT_MATRIX1 Register
2322212019181716
IN11_COMIN10_COMIN9_COMIN8_COMIN7_COMIN6_COMIN5_COMIN4_COM
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
IN3_COMIN2_COMIN1_COMIN0_COMINMAT_15_IN9INMAT_15_IN8INMAT_15_IN7INMAT_15_IN6
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INMAT_15_IN5INMAT_15_IN4INMAT_14_IN9INMAT_14_IN8INMAT_14_IN7INMAT_14_IN6INMAT_14_IN5INMAT_14_IN4
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only
Table 8-20 IN_STAT_MATRIX1 Register Field Descriptions
BitFieldTypeResetDescription
23IN11_COMR0h

0h = Input IN11 below threshold THRES_COM

1h = Input IN11 equal to or above threshold THRES_COM

22IN10_COMR0h

0h = Input IN10 below threshold THRES_COM

1h = Input IN10 equal to or above threshold THRES_COM

21IN9_COMR0h

0h = Input IN9 below threshold THRES_COM

1h = Input IN9 equal to or above threshold THRES_COM

20IN8_COMR0h

0h = Input IN8 below threshold THRES_COM

1h = Input IN8 equal to or above threshold THRES_COM

19IN7_COMR0h

0h = Input IN7 below threshold THRES_COM

1h = Input IN7 equal to or above threshold THRES_COM

18IN6_COMR0h

0h = Input IN6 below threshold THRES_COM

1h = Input IN6 equal to or above threshold THRES_COM

17IN5_COMR0h

0h = Input IN5 below threshold THRES_COM

1h = Input IN5 equal to or above threshold THRES_COM

16IN4_COMR0h

0h = Input IN4 below threshold THRES_COM

1h = Input IN4 equal to or above threshold THRES_COM

15IN3_COMR0h

0h = Input IN3 below threshold THRES_COM

1h = Input IN3 equal to or above threshold THRES_COM

14IN2_COMR0h

0h = Input IN2 below threshold THRES_COM

1h = Input IN2 equal to or above threshold THRES_COM

13IN1_COMR0h

0h = Input IN1 below threshold THRES_COM

1h = Input IN1 equal to or above threshold THRES_COM

12IN0_COMR0h

0h = Input IN0 below threshold THRES_COM

1h = Input IN0 equal to or above threshold THRES_COM

11INMAT_15_IN9R0h

0h = Input IN15 below threshold while IN9 pulled to GND

1h = Input IN15 above threshold while IN9 pulled to GND

10INMAT_15_IN8R0h

0h = Input IN15 below threshold while IN8 pulled to GND

1h = Input IN15 above threshold while IN8 pulled to GND

9INMAT_15_IN7R0h

0h = Input IN15 below threshold while IN7 pulled to GND

1h = Input IN15 above threshold while IN7 pulled to GND

8INMAT_15_IN6R0h

0h = Input IN15 below threshold while IN6 pulled to GND

1h = Input IN15 above threshold while IN6 pulled to GND

7INMAT_15_IN5R0h

0h = Input IN15 below threshold while IN5 pulled to GND

1h = Input IN15 above threshold while IN5 pulled to GND

6INMAT_15_IN4R0h

0h = Input IN15 below threshold while IN4 pulled to GND

1h = Input IN15 above threshold while IN4 pulled to GND

5INMAT_14_IN9R0h

0h = Input IN14 below threshold while IN9 pulled to GND

1h = Input IN14 above threshold while IN9 pulled to GND

4INMAT_14_IN8R0h

0h = Input IN14 below threshold while IN8 pulled to GND

1h = Input IN14 above threshold while IN8 pulled to GND

3INMAT_14_IN7R0h

0h = Input IN14 below threshold while IN7 pulled to GND

1h = Input IN14 above threshold while IN7 pulled to GND

2INMAT_14_IN6R0h

0h = Input IN14 below threshold while IN6 pulled to GND

1h = Input IN14 above threshold while IN6 pulled to GND

1INMAT_14_IN5R0h

0h = Input IN14 below threshold while IN5 pulled to GND

1h = Input IN14 above threshold while IN5 pulled to GND

0INMAT_14_IN4R0h

0h = Input IN14 below threshold while IN4 pulled to GND

1h = Input IN14 above threshold while IN4 pulled to GND

8.6.10 ANA_STAT0 Register (Offset = Ah) [Reset = 0h]

ANA_STAT0 is shown in Figure 8-33 and described in Table 8-21.

Return to Summary Table.

Figure 8-33 ANA_STAT0 Register
23222120191817161514131211109876543210
RESERVEDIN1_ANAIN0_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-21 ANA_STAT0 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN1_ANAR0h

10-bits value of IN1

Bit 10: LSB

Bit 19: MSB

9-0IN0_ANAR0h

10-bits value of IN0

Bit 0: LSB

Bit 9: MSB

8.6.11 ANA_STAT1 Register (Offset = Bh) [Reset = 0h]

ANA_STAT1 is shown in Figure 8-34 and described in Table 8-22.

Return to Summary Table.

Figure 8-34 ANA_STAT1 Register
23222120191817161514131211109876543210
RESERVEDIN5_ANAIN4_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-22 ANA_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN3_ANAR0h

10-bits value of IN3

Bit 10: LSB

Bit 19: MSB

9-0IN2_ANAR0h

10-bits value of IN2

Bit 0: LSB

Bit 9: MSB

8.6.12 ANA_STAT2 Register (Offset = Ch) [Reset = 0h]

ANA_STAT2 is shown in Figure 8-35 and described in Table 8-23.

Return to Summary Table.

Figure 8-35 ANA_STAT2 Register
23222120191817161514131211109876543210
RESERVEDIN5_ANAIN4_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-23 ANA_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN5_ANAR0h

10-bits value of IN5

Bit 10: LSB

Bit 19: MSB

9-0IN4_ANAR0h

10-bits value of IN4

Bit 0: LSB

Bit 9: MSB

8.6.13 ANA_STAT3 Register (Offset = Dh) [Reset = 0h]

ANA_STAT3 is shown in Figure 8-36 and described in Table 8-24.

Return to Summary Table.

Figure 8-36 ANA_STAT3 Register
23222120191817161514131211109876543210
RESERVEDIN7_ANAIN6_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-24 ANA_STAT3 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN7_ANAR0h

10-bits value of IN7

Bit 10: LSB

Bit 19: MSB

9-0IN6_ANAR0h

10-bits value of IN6

Bit 0: LSB

Bit 9: MSB

8.6.14 ANA_STAT4 Register (Offset = Eh) [Reset = 0h]

ANA_STAT4 is shown in Figure 8-37 and described in Table 8-25.

Return to Summary Table.

Figure 8-37 ANA_STAT4 Register
23222120191817161514131211109876543210
RESERVEDIN9_ANAIN8_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-25 ANA_STAT4 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN9_ANAR0h

10-bits value of IN9

Bit 10: LSB

Bit 19: MSB

9-0IN8_ANAR0h

10-bits value of IN8

Bit 0: LSB

Bit 9: MSB

8.6.15 ANA_STAT5 Register (Offset = Fh) [Reset = 0h]

ANA_STAT5 is shown in Figure 8-38 and described in Table 8-26.

Return to Summary Table.

Figure 8-38 ANA_STAT5 Register
23222120191817161514131211109876543210
RESERVEDIN11_ANAIN10_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-26 ANA_STAT5 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN11_ANAR0h

10-bits value of IN11

Bit 10: LSB

Bit 19: MSB

9-0IN10_ANAR0h

10-bits value of IN10

Bit 0: LSB

Bit 9: MSB

8.6.16 ANA_STAT6 Register (Offset = 10h) [reset = 0h]

ANA_STAT6 is shown in Figure 8-39 and described in Table 8-27.

Return to Summary Table.

Figure 8-39 ANA_STAT6 Register
23222120191817161514131211109876543210
RESERVEDIN13_ANAIN12_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-27 ANA_STAT6 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN13_ANAR0h

10-bits value of IN13

Bit 10: LSB

Bit 19: MSB

9-0IN12_ANAR0h

10-bits value of IN12

Bit 0: LSB

Bit 9: MSB

8.6.17 ANA_STAT7 Register (Offset = 11h) [Reset = 0h]

ANA_STAT7 is shown in Figure 8-40 and described in Table 8-28.

Return to Summary Table.

Figure 8-40 ANA_STAT7 Register
23222120191817161514131211109876543210
RESERVEDIN15_ANAIN14_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-28 ANA_STAT7 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN15_ANAR0h

10-bits value of IN15

Bit 10: LSB

Bit 19: MSB

9-0IN14_ANAR0h

10-bits value of IN14

Bit 0: LSB

Bit 9: MSB

8.6.18 ANA_STAT8 Register (Offset = 12h) [Reset = 0h]

ANA_STAT8 is shown in Figure 8-41 and described in Table 8-29.

Return to Summary Table.

Figure 8-41 ANA_STAT8 Register
23222120191817161514131211109876543210
RESERVEDIN17_ANAIN16_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-29 ANA_STAT8 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN17_ANAR0h

10-bits value of IN17

Bit 10: LSB

Bit 19: MSB

9-0IN16_ANAR0h

10-bits value of IN16

Bit 0: LSB

Bit 9: MSB

8.6.19 ANA_STAT9 Register (Offset = 13h) [Reset = 0h]

ANA_STAT9 is shown in Figure 8-42 and described in Table 8-30.

Return to Summary Table.

Figure 8-42 ANA_STAT9 Register
23222120191817161514131211109876543210
RESERVEDIN19_ANAIN18_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-30 ANA_STAT9 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN19_ANAR0h

10-bits value of IN19

Bit 10: LSB

Bit 19: MSB

9-0IN18_ANAR0h

10-bits value of IN18

Bit 0: LSB

Bit 9: MSB

8.6.20 ANA_STAT10 Register (Offset = 14h) [Reset = 0h]

ANA_STAT10 is shown in Figure 8-43 and described in Table 8-31.

Return to Summary Table.

Figure 8-43 ANA_STAT10 Register
23222120191817161514131211109876543210
RESERVEDIN21_ANAIN20_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-31 ANA_STAT10 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN21_ANAR0h

10-bits value of IN21

Bit 10: LSB

Bit 19: MSB

9-0IN20_ANAR0h

10-bits value of IN20

Bit 0: LSB

Bit 9: MSB

8.6.21 ANA_STAT11 Register (Offset = 15h) [Reset = 0h]

ANA_STAT11 is shown in Figure 8-44 and described in Table 8-32.

Return to Summary Table.

Figure 8-44 ANA_STAT11 Register
23222120191817161514131211109876543210
RESERVEDIN23_ANAIN22_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-32 ANA_STAT11 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10IN23_ANAR0h

10-bits value of IN23

Bit 10: LSB

Bit 19: MSB

9-0IN22_ANAR0h

10-bits value of IN22

Bit 0: LSB

Bit 9: MSB

8.6.22 ANA_STAT12 Register (Offset = 16h) [Reset = 0h]

ANA_STAT12 is shown in Figure 8-45 and described in Table 8-33.

Return to Summary Table.

Figure 8-45 ANA_STAT12 Register
23222120191817161514131211109876543210
RESERVEDADC_SELF_ANAVS_ANA
R-0hR-0hR-0h
LEGEND: R = Read only
Table 8-33 ANA_STAT12 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10ADC_SELF_ANAR0h

10-bits value of the ADC self-diagnosis

Bit 10: LSB

Bit 19: MSB

9-0VS_ANAR0h

10-bits value of VS measurement

Bit 0: LSB

Bit 9: MSB

8.6.23 CONFIG Register (Offset = 1Ah) [Reset = 0h]

CONFIG is shown in Figure 8-46 and described in Table 8-34.

Return to Summary Table.

Figure 8-46 CONFIG Register
2322212019181716
VS_RATIOADC_DIAG_TWET_D_IN3_ENWET_D_IN2_ENWET_D_IN1_ENWET_D_IN0_ENVS_MEAS_ENTW_CUR_DIS_CSI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DET_FILTERTW_CUR_DIS_CSOINT_CONFIGTRIGGERPOLL_ENCRC_TPOLL_ACT_TIME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
POLL_ACT_TIMEPOLL_TIMERESET
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-34 CONFIG Register Field Descriptions
BitFieldTypeResetDescription
23VS_RATIOR/W0h

0h = Use voltage divider factor of 3 for the VS measurement

1h = Use voltage divider factor of 10 for the VS measurement

22ADC_DIAG_TR/W0h

For detailed descriptions for the ADC self-diagnostic feature, refer to section ADC Self-Diagnostic

0h = Disable ADC self-diagnostic feature

1h = Enable ADC self-diagnostic feature

21WET_D_IN3_ENR/W0h

0h = Disable wetting current diagnostic for input IN3

1h = Enable wetting current diagnostic for input IN3

20WET_D_IN2_ENR/W0h

0h = Disable wetting current diagnostic for input IN2

1h = Enable wetting current diagnostic for input IN2

19WET_D_IN1_ENR/W0h

0h = Disable wetting current diagnostic for input IN1

1h = Enable wetting current diagnostic for input IN1

18WET_D_IN0_ENR/W0h

0h = Disable wetting current diagnostic for input IN0

1h = Enable wetting current diagnostic for input IN0

17VS_MEAS_ENR/W0h

For detailed descriptions for the VS measurement, refer to section VS Measurement.

0h = Disable VS measurement at the end of every polling cycle

1h = Enable VS measurement at the end of every polling cycle

16TW_CUR_DIS_CSIR/W0h

0h = Enable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSI.

1h = Disable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSI.

15-14DET_FILTERR/W0h

For detailed descriptions for the detection filter, refer to section Detection Filter.

0h = every sample is valid and taken for threshold evaluation

1h = 2 consecutive and equal samples required to be valid data

2h = 3 consecutive and equal samples required to be valid data

3h = 4 consecutive and equal samples required to be valid data

13TW_CUR_DIS_CSOR/W0h

0h = Enable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSO.

1h = Disable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSO.

12INT_CONFIGR/W0h

For detailed descriptions for the INT pin assertion scheme, refer to section Interrupt Generation and /INT Assertion.

0h = INT pin assertion scheme set to static

1h = INT pin assertion scheme set to dynamic

11TRIGGERR/W0h

When the TRIGGER bit is set to logic 1, normal device operation (wetting current activation and polling) starts. To stop device operation and keep the device in an idle state, de-assert this bit to 0. After device normal operation is triggered, if at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER to logic 0 to stop device operation. Once the re-configuration is completed, the microcontroller can set the TRIGGER bit back to logic 1 to re-start device operation. If re-configuration is done on the fly without first stopping the device operation, false switch status could be reported and accidental interrupt might be issued. The following register bits are the exception and can be configured when TRIGGER bit is set to logic 1:

  • TRIGGER (bit 11 of the CONFIG register)
  • CRC_T (bit 9 of the CONFIG register)
  • RESET (bit 0 of the CONFIG register)
  • The CCP_CFG1 register

0h = Stop TIC12400-Q1 from normal operation.

1h = Trigger TIC12400-Q1 from normal operation.

10POLL_ENR/W0h

0h = Polling disabled. Device operates in continuous mode.

1h = Polling enabled and the device operates in one of the polling modes.

9CRC_TR/W0h

Set this bit to 1 to trigger a CRC calculation on all the configuration register bits. Once triggered, it is strongly recommended the SPI controller does not change the content of the configuration registers until the CRC calculation is completed to avoid erroneous CRC calculation result. The TIC12400-Q1 sets the CRC_CALC interrupt bit and asserts the INT pin low when the CRC calculation is completed. The calculated result will be available in the CRC register. This bit self-clears back to 0 after CRC calculation is executed.

0h = no CRC calculation triggered.

1h = trigger CRC calculation.

8-5POLL_ACT_TIMER/W0h

0h = 64 μs

1h = 128 μs

2h = 192 μs

3h = 256 μs

4h = 320 μs

5h = 384 μs

6h = 448 μs

7h = 512 μs

8h = 640 μs

9h = 768 μs

Ah = 896 μs

Bh = 1024 μs

Ch = 2048 μs

Dh-15h = 512 μs (most frequently-used setting)

4-1POLL_TIMER/W0h

0h = 2 ms

1h = 4 ms

2h = 8 ms

3h = 16 ms

4h = 32 ms

5h = 48 ms

6h = 64 ms

7h = 128 ms

8h = 256 ms

9h = 512 ms

Ah = 1024 ms

Bh = 2048 ms

Ch = 4096 ms

Dh-15h = 8 ms (most frequently-used setting)

0RESETR/W0h

0h = No reset.

1h = Trigger software reset of the device.

8.6.24 IN_EN Register (Offset = 1Bh) [Reset = 0h]

IN_EN is shown in Figure 8-47 and described in Table 8-35.

Return to Summary Table.

Figure 8-47 IN_EN Register
2322212019181716
IN_EN_23IN_EN_22IN_EN_21IN_EN_20IN_EN_19IN_EN_18IN_EN_17IN_EN_16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
IN_EN_15IN_EN_14IN_EN_13IN_EN_12IN_EN_11IN_EN_10IN_EN_9IN_EN_8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
IN_EN_7IN_EN_6IN_EN_5IN_EN_4IN_EN_3IN_EN_2IN_EN_1IN_EN_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-35 IN_EN Register Field Descriptions
BitFieldTypeResetDescription
23IN_EN_23R/W0h

0h = Input channel IN23 disabled. Polling sequence skips this channel

1h = Input channel IN23 enabled.

22IN_EN_22R/W0h

0h = Input channel IN22 disabled. Polling sequence skips this channel

1h = Input channel IN22 enabled.

21IN_EN_21R/W0h

0h = Input channel IN21 disabled. Polling sequence skips this channel

1h = Input channel IN21 enabled.

20IN_EN_20R/W0h

0h = Input channel IN20 disabled. Polling sequence skips this channel

1h = Input channel IN20 enabled.

19IN_EN_19R/W0h

0h = Input channel IN19 disabled. Polling sequence skips this channel

1h = Input channel IN19 enabled.

18IN_EN_18R/W0h

0h = Input channel IN18 disabled. Polling sequence skips this channel

1h = Input channel IN18 enabled.

17IN_EN_17R/W0h

0h = Input channel IN17 disabled. Polling sequence skips this channel

1h = Input channel IN17 enabled.

16IN_EN_16R/W0h

0h = Input channel IN16 disabled. Polling sequence skips this channel

1h = Input channel IN16 enabled.

15IN_EN_15R/W0h

0h = Input channel IN15 disabled. Polling sequence skips this channel

1h = Input channel IN15 enabled.

14IN_EN_14R/W0h

0h = Input channel IN14 disabled. Polling sequence skips this channel

1h = Input channel IN14 enabled.

13IN_EN_13R/W0h

0h = Input channel IN13 disabled. Polling sequence skips this channel

1h = Input channel IN13 enabled.

12IN_EN_12R/W0h

0h = Input channel IN12 disabled. Polling sequence skips this channel

1h = Input channel IN12 enabled.

11IN_EN_11R/W0h

0h = Input channel IN11 disabled. Polling sequence skips this channel

1h = Input channel IN11 enabled.

10IN_EN_10R/W0h

0h = Input channel IN10 disabled. Polling sequence skips this channel

1h = Input channel IN10 enabled.

9IN_EN_9R/W0h

0h = Input channel IN9 disabled. Polling sequence skips this channel

1h = Input channel IN9 enabled.

8IN_EN_8R/W0h

0h = Input channel IN8 disabled. Polling sequence skips this channel

1h = Input channel IN8 enabled.

7IN_EN_7R/W0h

0h = Input channel IN7 disabled. Polling sequence skips this channel

1h = Input channel IN7 enabled.

6IN_EN_6R/W0h

0h = Input channel IN6 disabled. Polling sequence skips this channel

1h = Input channel IN6 enabled.

5IN_EN_5R/W0h

0h = Input channel IN5 disabled. Polling sequence skips this channel

1h = Input channel IN5 enabled.

4IN_EN_4R/W0h

0h = Input channel IN4 disabled. Polling sequence skips this channel

1h = Input channel IN4 enabled.

3IN_EN_3R/W0h

0h = Input channel IN3 disabled. Polling sequence skips this channel

1h = Input channel IN3 enabled.

2IN_EN_2R/W0h

0h = Input channel IN2 disabled. Polling sequence skips this channel

1h = Input channel IN2 enabled.

1IN_EN_1R/W0h

0h = Input channel IN1 disabled. Polling sequence skips this channel

1h = Input channel IN1 enabled.

0IN_EN_0R/W0h

0h = Input channel IN0 disabled. Polling sequence skips this channel

1h = Input channel IN0 enabled.

8.6.25 CS_SELECT Register (Offset = 1Ch) [Reset = 0h]

CS_SELECT is shown in Figure 8-48 and described in Table 8-36.

Return to Summary Table.

Figure 8-48 CS_SELECT Register
232221201918171615141312
RESERVED
R-0h
11109876543210
RESERVEDCS_IN9CS_IN8CS_IN7CS_IN6CS_IN5CS_IN4CS_IN3CS_IN2CS_IN1CS_IN0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-36 CS_SELECT Register Field Descriptions
BitFieldTypeResetDescription
23-10RESERVEDR0h

Reserved

9CS_IN9R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

8CS_IN8R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

7CS_IN7R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

6CS_IN6R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

5CS_IN5R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

4CS_IN4R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

3CS_IN3R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

2CS_IN2R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

1CS_IN1R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0CS_IN0R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

8.6.26 WC_CFG0 Register (Offset = 1Dh) [Reset = 0h]

WC_CFG0 is shown in Figure 8-49 and described in Table 8-37.

Return to Summary Table.

Figure 8-49 WC_CFG0 Register
232221201918171615141312
WC_IN11WC_IN10WC_IN8_IN9WC_IN6_IN7
R/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
WC_IN5WC_IN4WC_IN2_IN3WC_IN0_IN1
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-37 WC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-21WC_IN11R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

20-18WC_IN10R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

17-15WC_IN8_IN9R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

14-12WC_IN6_IN7R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

11-9WC_IN5R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

8-6WC_IN4R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

5-3WC_IN2_IN3R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

2-0WC_IN0_IN1R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

8.6.27 WC_CFG1 Register (Offset = 1Eh) [Reset = 0h]

WC_CFG1 is shown in Figure 8-50 and described in Table 8-38.

Return to Summary Table.

Figure 8-50 WC_CFG1 Register
232221201918171615141312
RESERVEDAUTO_SCALE_DIS_CSIAUTO_SCALE_DIS_CSOWC_IN23WC_IN22WC_IN20_IN21
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
WC_IN18_IN19WC_IN16_IN17WC_IN14_IN15WC_IN12_IN13
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-38 WC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
23RESERVEDR0h

Reserved

22AUTO_SCALE_DIS_CSIR/W0h

0h = Enable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CSI

1h = Disable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CS

For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling.

21AUTO_SCALE_DIS_CSOR/W0h

0h = Enable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CSO

1h = Disable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CSO

For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling.

20-18WC_IN23R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

17-15WC_IN22R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

14-12WC_IN20_IN21R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

11-9WC_IN18_IN19R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

8-6WC_IN16_IN17R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

5-3WC_IN14_IN15R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

2-0WC_IN12_IN13R/W0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

8.6.28 CCP_CFG0 Register (Offset = 1Fh) [Reset = 0h]

CCP_CFG0 is shown in Figure 8-51 and described in Table 8-39.

Return to Summary Table.

Figure 8-51 CCP_CFG0 Register
232221201918171615141312
RESERVED
R-0h
11109876543210
RESERVEDCCP_TIMEWC_CCP3WC_CCP2WC_CCP1WC_CCP0
R-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-39 CCP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-7RESERVEDR0h

Reserved

6-4CCP_TIMER/W0h

Wetting current activation time in CCP mode

0h = 64 μs

1h = 128 μs

2h = 192 μs

3h = 256 μs

4h = 320 μs

5h = 384 μs

6h = 448 μs

7h = 512 μs

3WC_CCP3R/W0h

Wetting current setting for IN18 to IN23 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

2WC_CCP2R/W0h

Wetting current setting for IN12 to IN17 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

1WC_CCP1R/W0h

Wetting current setting for IN6 to IN11 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

0WC_CCP0R/W0h

Wetting current setting for IN0 to IN5 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

8.6.29 CCP_CFG1 Register (Offset = 20h) [Reset = 0h]

CCP_CFG1 is shown in Figure 8-52 and described in Table 8-40.

Return to Summary Table.

Figure 8-52 CCP_CFG1 Register
2322212019181716
CCP_IN23CCP_IN22CCP_IN21CCP_IN20CCP_IN19CCP_IN18CCP_IN17CCP_IN16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CCP_IN15CCP_IN14CCP_IN13CCP_IN12CCP_IN11CCP_IN10CCP_IN9CCP_IN8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CCP_IN7CCP_IN6CCP_IN5CCP_IN4CCP_IN3CCP_IN2CCP_IN1CCP_IN0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-40 CCP_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
23CCP_IN23R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

22CCP_IN22R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

21CCP_IN21R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

20CCP_IN20R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

19CCP_IN19R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

18CCP_IN18R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

17CCP_IN17R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

16CCP_IN16R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

15CCP_IN15R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

14CCP_IN14R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

13CCP_IN13R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

12CCP_IN12R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

11CCP_IN11R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

10CCP_IN10R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

9CCP_IN9R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

8CCP_IN8R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

7CCP_IN7R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

6CCP_IN6R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

5CCP_IN5R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

4CCP_IN4R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

3CCP_IN3R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

2CCP_IN2R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

1CCP_IN1R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

0CCP_IN0R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

8.6.30 THRES_COMP Register (Offset = 21h) [Reset = 0h]

THRES_COMP is shown in Figure 8-53 and described in Table 8-41.

Return to Summary Table.

Figure 8-53 THRES_COMP Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRES_COMP_IN20_IN23THRES_COMP_IN16_IN19
R-0hR/W-0hR/W-0h
76543210
THRES_COMP_IN12_IN15THRES_COMP_IN8_IN11THRES_COMP_IN4_IN7THRES_COMP_IN0_IN3
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-41 THRES_COMP Register Field Descriptions
BitFieldTypeResetDescription
23-12RESERVEDR0h

Reserved

11-10THRES_COMP_IN20_IN23R/W0h

These 2 bits configure the comparator thresholds for input channels IN20 to IN23.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

9-8THRES_COMP_IN16_IN19R/W0h

These 2 bits configure the comparator thresholds for input channels IN16 to IN19.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

7-6THRES_COMP_IN12_IN15R/W0h

These 2 bits configure the comparator thresholds for input channels IN12 to IN15.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

5-4THRES_COMP_IN8_IN11R/W0h

These 2 bits configure the comparator thresholds for input channels IN8 to IN11.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

3-2THRES_COMP_IN4_IN7R/W0h

These 2 bits configure the comparator thresholds for input channels IN4 to IN7

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

1-0THRES_COMP_IN0_IN3R/W0h

These 2 bits configure the comparator thresholds for input channels IN0 to IN3

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

8.6.31 INT_EN_COMP1 Register (Offset = 22h) [Reset = 0h]

INT_EN_COMP1 is shown in Figure 8-54 and described in Table 8-42.

Return to Summary Table.

Figure 8-54 INT_EN_COMP1 Register
232221201918171615141312
INC_EN_11INC_EN_10INC_EN_9INC_EN_8INC_EN_7INC_EN_6
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
INC_EN_5INC_EN_4INC_EN_3INC_EN_2INC_EN_1INC_EN_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-42 INT_EN_COMP1 Register Field Descriptions
BitFieldTypeResetDescription
23-22INC_EN_11R/W0h

0h = no interrupt generation for IN11.

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN11.

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN11.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN11.

21-20INC_EN_10R/W0h

0h = no interrupt generation for IN10

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN10.

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN10.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN10.

19-18INC_EN_9R/W0h

0h = no interrupt generation for IN9.

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN9.

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN9.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN9.

17-16INC_EN_8R/W0h

0h = no interrupt generation for IN8.

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN8.

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN8.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN8.

15-14INC_EN_7R/W0h

0h = no interrupt generation for IN7.

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN7.

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN7.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN7.

13-12INC_EN_6R/W0h

0h = no interrupt generation for IN6.

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN6.

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN6.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN6.

11-10INC_EN_5R/W0h

0h = no interrupt generation for IN5.

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN5.

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN5.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN5.

9-8INC_EN_4R/W0h

0h = no interrupt generation for IN4.

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN4.

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN4.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN4.

7-6INC_EN_3R/W0h

0h = no interrupt generation for IN3.

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN3.

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN3.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN3.

5-4INC_EN_2R/W0h

0h = no interrupt generation for IN2.

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN2.

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN2.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN2.

3-2INC_EN_1R/W0h

0h = no interrupt generation for IN1.

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN1.

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN1.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN1.

1-0INC_EN_0R/W0h

0h = no interrupt generation for IN0.

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN0.

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN0.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN0.

8.6.32 INT_EN_COMP2 Register (Offset = 23h) [Reset = 0h]

INT_EN_COMP2 is shown in Figure 8-55 and described in Table 8-43.

Return to Summary Table.

Figure 8-55 INT_EN_COMP2 Register
232221201918171615141312
INC_EN_23INC_EN_22INC_EN_21INC_EN_20INC_EN_19INC_EN_18
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
INC_EN_17INC_EN_16INC_EN_15INC_EN_14INC_EN_13INC_EN_12
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-43 INT_EN_COMP2 Register Field Descriptions
BitFieldTypeResetDescription
23-22INC_EN_23R/W0h

0h = no interrupt generation for IN23.

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN23.

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN23.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN23.

21-20INC_EN_22R/W0h

0h = no interrupt generation for IN22.

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN22.

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN22.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN22.

19-18INC_EN_21R/W0h

0h = no interrupt generation for IN21.

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN21.

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN21.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN21.

17-16INC_EN_20R/W0h

0h = no interrupt generation for IN20.

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN20.

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN20.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN20.

15-14INC_EN_19R/W0h

0h = no interrupt generation for IN19.

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN19.

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN19.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN19.

13-12INC_EN_18R/W0h

0h = no interrupt generation for IN18.

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN18.

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN18.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN18.

11-10INC_EN_17R/W0h

0h = no interrupt generation for IN17.

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN17.

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN17.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN17.

9-8INC_EN_16R/W0h

0h = no interrupt generation for IN16.

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN16.

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN16.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN16.

7-6INC_EN_15R/W0h

0h = no interrupt generation for IN15.

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN15.

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN15.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN15.

5-4INC_EN_14R/W0h

0h = no interrupt generation for IN14.

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN14.

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN14.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN14.

3-2INC_EN_13R/W0h

0h = no interrupt generation for IN13.

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN13.

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN13.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN13.

1-0INC_EN_12R/W0h

0h = no interrupt generation for IN12.

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN12.

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN12.

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN12.

8.6.33 INT_EN_CFG0 Register (Offset = 24h) [Reset = 0h]

INT_EN_CFG0 is shown in Figure 8-56 and described in Table 8-44.

Return to Summary Table.

Figure 8-56 INT_EN_CFG0 Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDADC_DIAG_ENWET_DIAG_ENVS1_ENVS0_EN
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CRC_CALC_ENUV_ENOV_ENTW_ENTSD_ENSSC_ENPRTY_FAIL_ENSPI_FAIL_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-44 INT_EN_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-12RESERVEDR0h

Reserved

11ADC_DIAG_ENR/W0h

0h = INT pin assertion due to ADC error disabled.

1h = INT pin assertion due to ADC error enabled.

10WET_DIAG_ENR/W0h

0h = INT pin assertion due to wetting current error disabled.

1h = INT pin assertion due to wetting current error enabled.

9VS1_ENR/W0h

0h = INT pin assertion due to VS1 threshold crossing disabled.

1h = INT pin assertion due to VS1 threshold crossing enabled.

8VS0_ENR/W0h

0h = INT pin assertion due to VS0 threshold crossing disabled.

1h = INT pin assertion due to VS0 threshold crossing enabled.

7CRC_CALC_ENR/W0h

0h = INT pin assertion due to CRC calculation completion disabled.

1h = INT pin assertion due to CRC calculation completion enabled.

6UV_ENR/W0h

0h = INT pin assertion due to UV event disabled.

1h = INT pin assertion due to UV event enabled.

5OV_ENR/W0h

0h = INT pin assertion due to OV event disabled.

1h = INT pin assertion due to OV event enabled.

4TW_ENR/W0h

0h = INT pin assertion due to TW event disabled.

1h = INT pin assertion due to TW event enabled.

3TSD_ENR/W0h

0h = INT pin assertion due to TSD event disabled.

1h = INT pin assertion due to TSD event enabled.

2SSC_ENR/W0h

0h = INT pin assertion due to SSC event disabled.

1h = INT pin assertion due to SSC event enabled.

1PRTY_FAIL_ENR/W0h

0h = INT pin assertion due to parity fail event disabled.

1h = INT pin assertion due to parity fail event enabled.

0SPI_FAIL_ENR/W0h

0h = INT pin assertion due to SPI fail event disabled.

1h = INT pin assertion due to SPI fail event enabled.

8.6.34 INT_EN_CFG1 Register (Offset = 25h) [Reset = 0h]

INT_EN_CFG1 is shown in Figure 8-57 and described in Table 8-45.

Return to Summary Table.

Figure 8-57 INT_EN_CFG1 Register
232221201918171615141312
IN11_ENIN10_ENIN9_ENIN8_ENIN7_ENIN6_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
IN5_ENIN4_ENIN3_ENIN2_ENIN1_ENIN0_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-45 INT_EN_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
23-22IN11_ENR/W0h

0h = no interrupt generation for IN11.

1h = interrupt generation on rising edge above THRESx for IN11.

2h = interrupt generation on falling edge below THRESx for IN11.

3h = interrupt generation on falling and rising edge of THRESx for IN11.

21-20IN10_ENR/W0h

0h = no interrupt generation for IN10.

1h = interrupt generation on rising edge above THRESx for IN10.

2h = interrupt generation on falling edge below THRESx for IN10.

3h = interrupt generation on falling and rising edge of THRESx for IN10.

19-18IN9_ENR/W0h

0h = no interrupt generation for IN9.

1h = interrupt generation on rising edge above THRESx for IN9.

2h = interrupt generation on falling edge below THRESx for IN9.

3h = interrupt generation on falling and rising edge of THRESx for IN9.

17-16IN8_ENR/W0h

0h = no interrupt generation for IN8.

1h = interrupt generation on rising edge above THRESx for IN8.

2h = interrupt generation on falling edge below THRESx for IN8.

3h = interrupt generation on falling and rising edge of THRESx for IN8.

15-14IN7_ENR/W0h

0h = no interrupt generation for IN7.

1h = interrupt generation on rising edge above THRESx for IN7.

2h = interrupt generation on falling edge below THRESx for IN7.

3h = interrupt generation on falling and rising edge of THRESx for IN7.

13-12IN6_ENR/W0h

0h = no interrupt generation for IN6.

1h = interrupt generation on rising edge above THRESx for IN6.

2h = interrupt generation on falling edge below THRESx for IN6.

3h = interrupt generation on falling and rising edge of THRESx for IN6.

11-10IN5_ENR/W0h

0h = no interrupt generation for IN5.

1h = interrupt generation on rising edge above THRESx for IN5.

2h = interrupt generation on falling edge below THRESx for IN5.

3h = interrupt generation on falling and rising edge of THRESx for IN5.

9-8IN4_ENR/W0h

0h = no interrupt generation for IN4.

1h = interrupt generation on rising edge above THRESx for IN4.

2h = interrupt generation on falling edge below THRESx for IN4.

3h = interrupt generation on falling and rising edge of THRESx for IN4.

7-6IN3_ENR/W0h

0h = no interrupt generation for IN3.

1h = interrupt generation on rising edge above THRESx for IN3.

2h = interrupt generation on falling edge below THRESx for IN3.

3h = interrupt generation on falling and rising edge of THRESx for IN3.

5-4IN2_ENR/W0h

0h = no interrupt generation for IN2.

1h = interrupt generation on rising edge above THRESx for IN2.

2h = interrupt generation on falling edge below THRESx for IN2.

3h = interrupt generation on falling and rising edge of THRESx for IN2.

3-2IN1_ENR/W0h

0h = no interrupt generation for IN1.

1h = interrupt generation on rising edge above THRESx for IN1.

2h = interrupt generation on falling edge below THRESx for IN1.

3h = interrupt generation on falling and rising edge of THRESx for IN1.

1-0IN0_ENR/W0h

0h = no interrupt generation for IN0.

1h = interrupt generation on rising edge above THRESx for IN0.

2h = interrupt generation on falling edge below THRESx for IN0.

3h = interrupt generation on falling and rising edge of THRESx for IN0.

8.6.35 INT_EN_CFG2 Register (Offset = 26h) [Reset = 0h]

INT_EN_CFG2 is shown in Figure 8-58 and described in Table 8-46.

Return to Summary Table.

Figure 8-58 INT_EN_CFG2 Register
232221201918171615141312
IN17_ENIN16_ENIN15_EN
R/W-0hR/W-0hR/W-0h
11109876543210
IN14_ENIN13_ENIN12_EN
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-46 INT_EN_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
23-20IN17_ENR/W0h

xx00: no interrupt generation for IN17 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN17.

xx10: interrupt generation on falling edge below THRES2A for IN17.

xx11: interrupt generation on falling and rising edge of THRES2A for IN17.

00xx: no interrupt generation for IN17 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN17.

10xx: interrupt generation on falling edge below THRES2B for IN17.

11xx: interrupt generation on falling and rising edge of THRES2B for IN17.

19-16IN16_ENR/W0h

xx00: no interrupt generation for IN16 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN16.

xx10: interrupt generation on falling edge below THRES2A for IN16.

xx11: interrupt generation on falling and rising edge of THRES2A for IN16.

00xx: no interrupt generation for IN16 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN16.

10xx: interrupt generation on falling edge below THRES2B for IN16.

11xx: interrupt generation on falling and rising edge of THRES2B for IN16.

15-12IN15_ENR/W0h

xx00: no interrupt generation for IN15 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN15.

xx10: interrupt generation on falling edge below THRES2A for IN15.

xx11: interrupt generation on falling and rising edge of THRES2A for IN15.

00xx: no interrupt generation for IN15 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN15.

10xx: interrupt generation on falling edge below THRES2B for IN15.

11xx: interrupt generation on falling and rising edge of THRES2B for IN15.

11-8IN14_ENR/W0h

xx00: no interrupt generation for IN14 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN14.

xx10: interrupt generation on falling edge below THRES2A for IN14.

xx11: interrupt generation on falling and rising edge of THRES2A for IN14.

00xx: no interrupt generation for IN14 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN14.

10xx: interrupt generation on falling edge below THRES2B for IN14.

11xx: interrupt generation on falling and rising edge of THRES2B for IN14.

7-4IN13_ENR/W0h

xx00: no interrupt generation for IN13 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN13.

xx10: interrupt generation on falling edge below THRES2A for IN13.

xx11: interrupt generation on falling and rising edge of THRES2A for IN13.

00xx: no interrupt generation for IN13 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN13.

10xx: interrupt generation on falling edge below THRES2B for IN13.

11xx: interrupt generation on falling and rising edge of THRES2B for IN13.

3-0IN12_ENR/W0h

xx00: no interrupt generation for IN12 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN12.

xx10: interrupt generation on falling edge below THRES2A for IN12.

xx11: interrupt generation on falling and rising edge of THRES2A for IN12.

00xx: no interrupt generation for IN12 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN12.

10xx: interrupt generation on falling edge below THRES2B for IN12.

11xx: interrupt generation on falling and rising edge of THRES2B for IN12.

8.6.36 INT_EN_CFG3 Register (Offset = 27h) [Reset = 0h]

INT_EN_CFG3 is shown in Figure 8-59 and described in Table 8-47.

Return to Summary Table.

Figure 8-59 INT_EN_CFG3 Register
232221201918171615141312
IN21_ENIN20_EN
R/W-0hR/W-0h
11109876543210
IN19_ENIN18_EN
R/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-47 INT_EN_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
23-18IN21_ENR/W0h

xxxx00: no interrupt generation for IN21 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for IN21

xxxx10: interrupt generation on falling edge below THRES3A for IN21

xxxx11: interrupt generation on falling and rising edge of THRES3A for IN21

xx00xx: no interrupt generation for IN21 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for IN21

xx10xx: interrupt generation on falling edge below THRES3B for IN21

xx11xx: interrupt generation on falling and rising edge of THRES3B for IN21

00xxxx: no interrupt generation for IN21 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for IN21

10xxxx: interrupt generation on falling edge below THRES3C for IN21

11xxxx: interrupt generation on falling and rising edge of THRES3C for IN21

17-12IN20_ENR/W0h

xxxx00: no interrupt generation for IN20 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for IN20

xxxx10: interrupt generation on falling edge below THRES3A for IN20

xxxx11: interrupt generation on falling and rising edge of THRES3A for IN20

xx00xx: no interrupt generation for IN20 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for IN20

xx10xx: interrupt generation on falling edge below THRES3B for IN20

xx11xx: interrupt generation on falling and rising edge of THRES3B for IN20

00xxxx: no interrupt generation for IN20 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for IN20

10xxxx: interrupt generation on falling edge below THRES3C for IN20

11xxxx: interrupt generation on falling and rising edge of THRES3C for IN20

11-6IN19_ENR/W0h

xxxx00: no interrupt generation for IN19 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for IN19

xxxx10: interrupt generation on falling edge below THRES3A for IN19

xxxx11: interrupt generation on falling and rising edge of THRES3A for IN19

xx00xx: no interrupt generation for IN19 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for IN19

xx10xx: interrupt generation on falling edge below THRES3B for IN19

xx11xx: interrupt generation on falling and rising edge of THRES3B for IN19

00xxxx: no interrupt generation for IN19 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for IN19

10xxxx: interrupt generation on falling edge below THRES3C for IN19

11xxxx: interrupt generation on falling and rising edge of THRES3C for IN19

5-0IN18_ENR/W0h

xxxx00: no interrupt generation for IN18 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for IN18

xxxx10: interrupt generation on falling edge below THRES3A for IN18

xxxx11: interrupt generation on falling and rising edge of THRES3A for IN18

xx00xx: no interrupt generation for IN18 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for IN18

xx10xx: interrupt generation on falling edge below THRES3B for IN18

xx11xx: interrupt generation on falling and rising edge of THRES3B for IN18

00xxxx: no interrupt generation for IN18 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for IN18

10xxxx: interrupt generation on falling edge below THRES3C for IN18

11xxxx: interrupt generation on falling and rising edge of THRES3C for IN18

8.6.37 INT_EN_CFG4 Register (Offset = 28h) [Reset = 0h]

INT_EN_CFG4 is shown in Figure 8-60 and described in Table 8-48.

Return to Summary Table.

Figure 8-60 INT_EN_CFG4 Register
232221201918171615141312
VS_TH1_ENVS_TH0_ENIN23_EN
R/W-0hR/W-0hR/W-0h
11109876543210
IN23_ENIN22_EN
R/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-48 INT_EN_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
23-20VS_TH1_ENR/W0h

xx00: no interrupt generation for VS w.r.t. VS1_THRES2A.

xx01: interrupt generation on rising edge above VS1_THRES2A for VS.

xx10: interrupt generation on falling edge below VS1_THRES2A for VS.

xx11: interrupt generation on falling and rising edge of VS1_THRES2A for VS.

00xx: no interrupt generation for VS w.r.t. VS1_THRES2B.

01xx: interrupt generation on rising edge above VS1_THRES2B for VS.

10xx: interrupt generation on falling edge below VS1_THRES2B for VS.

11xx: interrupt generation on falling and rising edge of VS1_THRES2B for VS.

19-16VS_TH0_ENR/W0h

xx00: no interrupt generation for VS w.r.t. VS0_THRES2A.

xx01: interrupt generation on rising edge above VS0_THRES2A for VS.

xx10: interrupt generation on falling edge below VS0_THRES2A for VS.

xx11: interrupt generation on falling and rising edge of VS0_THRES2A for VS.

00xx: no interrupt generation for VS w.r.t. VS0_THRES2B.

01xx: interrupt generation on rising edge above VS0_THRES2B for VS.

10xx: interrupt generation on falling edge below VS0_THRES2B for VS.

11xx: interrupt generation on falling and rising edge of VS0_THRES2B for VS.

15-6IN23_ENR/W0h

xxxxxxxx00: no interrupt generation for IN23 w.r.t. THRES3A.

xxxxxxxx01: interrupt generation on rising edge above THRES3A for IN23.

xxxxxxxx10: interrupt generation on falling edge below THRES3A for IN23.

xxxxxxxx11: interrupt generation on falling and rising edge of THRES3A for IN23.

xxxxxx00xx: no interrupt generation for IN23 w.r.t. THRES3B.

xxxxxx01xx: interrupt generation on rising edge above THRES3B for IN23.

xxxxxx10xx: interrupt generation on falling edge below THRES3B for IN23.

xxxxxx11xx: interrupt generation on falling and rising edge of THRES3B for IN23.

xxxx00xxxx: no interrupt generation for IN23 w.r.t. THRES3C.

xxxx01xxxx: interrupt generation on rising edge above THRES3C for IN23.

xxxx10xxxx: interrupt generation on falling edge below THRES3C for IN23.

xxxx11xxxx: interrupt generation on falling and rising edge of THRES3C for IN23.

xx00xxxxxx: no interrupt generation for IN23 w.r.t. THRES8.

xx01xxxxxx: interrupt generation on rising edge above THRES8 for IN23.

xx10xxxxxx: interrupt generation on falling edge below THRES8 for IN23.

xx11xxxxxx: interrupt generation on falling and rising edge of THRES8 for IN23.

00xxxxxxxx: no interrupt generation for IN23 w.r.t. THRES9.

01xxxxxxxx: interrupt generation on rising edge above THRES9 for IN23.

10xxxxxxxx: interrupt generation on falling edge below THRES9 for IN23.

11xxxxxxxx: interrupt generation on falling and rising edge of THRES9 for IN23.

5-0IN22_ENR/W0h

xxxx00: no interrupt generation for IN22 w.r.t. THRES3A.

xxxx01: interrupt generation on rising edge above THRES3A for IN22.

xxxx10: interrupt generation on falling edge below THRES3A for IN22.

xxxx11: interrupt generation on falling and rising edge of THRES3A for IN22.

xx00xx: no interrupt generation for IN22 w.r.t. THRES3B.

xx01xx: interrupt generation on rising edge above THRES3B for IN22.

xx10xx: interrupt generation on falling edge below THRES3B for IN22.

xx11xx: interrupt generation on falling and rising edge of THRES3B for IN22.

00xxxx: no interrupt generation for IN22 w.r.t. THRES3C.

01xxxx: interrupt generation on rising edge above THRES3C for IN22.

10xxxx: interrupt generation on falling edge below THRES3C for IN22.

11xxxx: interrupt generation on falling and rising edge of THRES3C for IN22.

8.6.38 THRES_CFG0 Register (Offset = 29h) [Reset = 0h]

THRES_CFG0 is shown in Figure 8-61 and described in Table 8-49.

Return to Summary Table.

Figure 8-61 THRES_CFG0 Register
23222120191817161514131211109876543210
RESERVEDTHRES1THRES0
R-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-49 THRES_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10THRES1R/W0h

10-bits value of threshold 1:

Bit10: LSB

Bit19: MSB

9-0THRES0R/W0h

10-bits value of threshold 0

Bit0: LSB

Bit9: MSB

8.6.39 THRES_CFG1 Register (Offset = 2Ah) [Reset = 0h]

THRES_CFG1 is shown in Figure 8-62 and described in Table 8-50.

Return to Summary Table.

Figure 8-62 THRES_CFG1 Register
23222120191817161514131211109876543210
RESERVEDTHRES3THRES2
R-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-50 THRES_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10THRES3R/W0h

10-bits value of threshold 3:

Bit10: LSB

Bit19: MSB

9-0THRES2R/W0h

10-bits value of threshold 2

Bit0: LSB

Bit9: MSB

8.6.40 THRES_CFG2 Register (Offset = 2Bh) [Reset = 0h]

THRES_CFG2 is shown in Figure 8-63 and described in Table 8-51.

Return to Summary Table.

Figure 8-63 THRES_CFG2 Register
23222120191817161514131211109876543210
RESERVEDTHRES5THRES4
R-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-51 THRES_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10THRES5R/W0h

10-bits value of threshold 5:

Bit10: LSB

Bit19: MSB

10-1THRES4R/W0h

10-bits value of threshold 4:

Bit0: LSB

Bit9: MSB

8.6.41 THRES_CFG3 Register (Offset = 2Ch) [Reset = X]

THRES_CFG3 is shown in Figure 8-64 and described in Table 8-52.

Return to Summary Table.

Figure 8-64 THRES_CFG3 Register
23222120191817161514131211109876543210
RESERVEDTHRES6THRES7
R-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-52 THRES_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10THRES7R/W0h

10-bits value of threshold 7:

Bit10: LSB

Bit19: MSB

9-0THRES6R/W0h

10-bits value of threshold 6:

Bit0: LSB

Bit9: MSB

8.6.42 THRES_CFG4 Register (Offset = 2Dh) [Reset = X]

THRES_CFG4 is shown in Figure 8-65 and described in Table 8-53.

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Figure 8-65 THRES_CFG4 Register
23222120191817161514131211109876543210
RESERVEDTHRES9THRES8
R-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-53 THRES_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
23-20RESERVEDR0h

Reserved

19-10THRES9R/W0h

10-bits value of threshold 9:

Bit10: LSB

Bit19: MSB

9-0THRES8R/W0h

10-bits value of threshold 8:

Bit0: LSB

Bit9: MSB

8.6.43 THRESMAP_CFG0 Register (Offset = 2Eh) [Reset = 0h]

THRESMAP_CFG0 is shown in Figure 8-66 and described in Table 8-54.

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Figure 8-66 THRESMAP_CFG0 Register
232221201918171615141312
THRESMAP_IN7THRESMAP_IN6THRESMAP_IN5THRESMAP_IN4
R/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
THRESMAP_IN3THRESMAP_IN2THRESMAP_IN1THRESMAP_IN0
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-54 THRESMAP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-21THRESMAP_IN7R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

20-18THRESMAP_IN6R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

17-15THRESMAP_IN5R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

14-12THRESMAP_IN4R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

11-9THRESMAP_IN3R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8-6THRESMAP_IN2R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

5-3THRESMAP_IN1R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

2-0THRESMAP_IN0R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8.6.44 THRESMAP_CFG1 Register (Offset = 2Fh) [Reset = 0h]

THRESMAP_CFG1 is shown in Figure 8-67 and described in Table 8-55.

Return to Summary Table.

Figure 8-67 THRESMAP_CFG1 Register
232221201918171615141312
RESERVEDTHRESMAP_IN12_IN17_THRES2BTHRESMAP_IN12_IN17_THRES2A
R/W-0hR/W-0hR/W-0h
11109876543210
THRESMAP_IN11THRESMAP_IN10THRESMAP_IN9THRESMAP_IN8
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-55 THRESMAP_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
23-18RESERVEDR0h

Reserved

17-15THRESMAP_IN12_IN17_THRES2BR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

14-12THRESMAP_IN12_IN17_THRES2AR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

11-9THRESMAP_IN11R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8-6THRESMAP_IN10R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

5-3THRESMAP_IN9R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

2-0THRESMAP_IN8R/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8.6.45 THRESMAP_CFG2 Register (Offset = 30h) [Reset = 0h]

THRESMAP_CFG2 is shown in Figure 8-68 and described in Table 8-56.

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Figure 8-68 THRESMAP_CFG2 Register
232221201918171615141312
RESERVEDTHRESMAP_VS1_THRES2BTHRESMAP_VS1_THRES2ATHRESMAP_VS0_THRES2B
R-0hR/W-0hR/W-0hR/W-0h
11109876543210
THRESMAP_VS0_THRES2ATHRESMAP_IN18_IN23_THRES3CTHRESMAP_IN18_IN23_THRES3BTHRESMAP_IN18_IN23_THRES3A
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-56 THRESMAP_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
23-21RESERVEDR0h

Reserved

20-18THRESMAP_VS1_THRES2BR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

17-15THRESMAP_VS1_THRES2AR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

14-12THRESMAP_VS0_THRES2BR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

11-9THRESMAP_VS0_THRES2AR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8-6THRESMAP_IN18_IN23_THRES3CR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

5-3THRESMAP_IN18_IN23_THRES3BR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

2-0THRESMAP_IN18_IN23_THRES3AR/W0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8.6.46 Matrix Register (Offset = 31h) [Reset = 0h]

Matrix is shown in Figure 8-69 and described in Table 8-57.

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Figure 8-69 Matrix Register
232221201918171615141312
RESERVEDIN_COM_ENTHRES_COM
R-0hR/W-0hR/W-0h
11109876543210
THRES_COMMATRIXPOLL_ACT_TIME_M
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 8-57 Matrix Register Field Descriptions
BitFieldTypeResetDescription
23-17RESERVEDR0h

Reserved

16-15IN_COM_ENR/W0h

0h = no interrupt generation for w.r.t. threshold THRES_COM

1h = interrupt generation on rising edge above threshold THRES_COM

2h = interrupt generation on falling edge below threshold THRES_COM

3h = interrupt generation on falling and rising edge of threshold THRES_COM

14-5THRES_COMR/W0h

10-bits value of threshold THRES_COM:

Bit5: LSB

Bit14: MSB

4-3MATRIXR/W0h

0h = no matrix, regular inputs only

1h = 4×4 matrix

2h = 5×5 matrix

3h = 6×6 matrix

2-0POLL_ACT_TIME_MR/W0h

Polling active time setting for the matrix inputs:

0h = 64 μs

1h = 128 μs

2h = 256 μs

3h = 384 μs

4h = 512 μs

5h = 768 μs

6h = 1024 μs

7h = 1360 μs

8.6.47 Mode Register (Offset = 32h) [Reset = 0h]

Mode is shown in Figure 8-70 and described in Table 8-58.

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Figure 8-70 Mode Register
232221201918171615141312
M_IN23M_IN22M_IN21M_IN20M_IN19M_IN18M_IN17M_IN16M_IN15M_IN14M_IN13M_IN12
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
M_IN11M_IN10M_IN9M_IN8M_IN7M_IN6M_IN5M_IN4M_IN3M_IN2M_IN1M_IN0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 8-58 Mode Register Field Descriptions
BitFieldTypeResetDescription
23M_IN23R/W0h

0h = comparator mode for IN23

1h = ADC mode for IN23

22M_IN22R/W0h

0h = comparator mode for IN22

1h = ADC mode for IN22

21M_IN21R/W0h

0h = comparator mode for IN21

1h = ADC mode for IN21

20M_IN20R/W0h

0h = comparator mode for IN20

1h = ADC mode for IN20

19M_IN19R/W0h

0h = comparator mode for IN19

1h = ADC mode for IN19

18M_IN18R/W0h

0h = comparator mode for IN18

1h = ADC mode for IN18

17M_IN17R/W0h

0h = comparator mode for IN17

1h = ADC mode for IN17

16M_IN16R/W0h

0h = comparator mode for IN16

1h = ADC mode for IN16

15M_IN15R/W0h

0h = comparator mode for IN15

1h = ADC mode for IN15

14M_IN14R/W0h

0h = comparator mode for IN14

1h = ADC mode for IN14

13M_IN13R/W0h

0h = comparator mode for IN13

1h = ADC mode for IN13

12M_IN12R/W0h

0h = comparator mode for IN12

1h = ADC mode for IN12

11M_IN11R/W0h

0h = comparator mode for IN11

1h = ADC mode for IN11

10M_IN10R/W0h

0h = comparator mode for IN10

1h = ADC mode for IN10

9M_IN9R/W0h

0h = comparator mode for IN9

1h = ADC mode for IN9

8M_IN8R/W0h

0h = comparator mode for IN8

1h = ADC mode for IN8

7M_IN7R/W0h

0h = comparator mode for IN7

1h = ADC mode for IN7

6M_IN6R/W0h

0h = comparator mode for IN6

1h = ADC mode for IN6

5M_IN5R/W0h

0h = comparator mode for IN5

1h = ADC mode for IN5

4M_IN4R/W0h

0h = comparator mode for IN4

1h = ADC mode for IN4

3M_IN3R/W0h

0h = comparator mode for IN3

1h = ADC mode for IN1

2M_IN2R/W0h

0h = comparator mode for IN2

1h = ADC mode for IN0

1M_IN1R/W0h

0h = comparator mode for IN1

1h = ADC mode for IN1

0M_IN0R/W0h

0h = comparator mode for IN0

1h = ADC mode for IN0