7.6.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]
DATA_CFG is shown in Figure 35 and described in Table 15.
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Figure 35. DATA_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
FIX_PAT |
RESERVED |
APPEND_STATUS[1:0] |
RESERVED |
R/W-0b |
R-0b |
R/W-0b |
R-0b |
|
Table 15. DATA_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
FIX_PAT |
R/W |
0b |
Device outputs fixed data bits. Helpful for debugging device communication.
0b = Normal operation.
1b = Device outputs a fixed code 0xA5A repeatitively when reading ADC data.
|
6 |
RESERVED |
R |
0b |
Reserved. Reads return 0b. |
5-4 |
APPEND_STATUS[1:0] |
R/W |
0b |
Append 4-bit channel ID to output data.
0b = Channel ID is not appended to ADC data.
1b = Channel ID is appended to ADC data.
|
3-0 |
RESERVED |
R |
0b |
Reserved. Reads return 0b. |