SLLSEC7A August   2012  – October 2015 TLK10034

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  LVCMOS Electrical Characteristics (VDDO)
    6. 4.6  High Speed Side Serial Transmitter Characteristics
    7. 4.7  High Speed Side Serial Receiver Characteristics
    8. 4.8  Low Speed Side Serial Transmitter Characteristics
    9. 4.9  Low Speed Side Serial Receiver Characteristics
    10. 4.10 Reference Clock Characteristics (REFCLK0P/N, REFCLK1P/N)
    11. 4.11 Differential Output Clock Characteristics (CLKOUTA/B/C/DP/N)
    12. 4.12 MDIO Timing Requirements
    13. 4.13 JTAG Timing Requirements
    14. 4.14 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagrams
    3. 5.3 Feature Description
      1. 5.3.1 10GBASE-KR Mode
        1. 5.3.1.1  10GBASE-KR Transmit Data Path Overview
        2. 5.3.1.2  10GBASE-KR Receive Data Path Overview
        3. 5.3.1.3  Channel Synchronization Block
        4. 5.3.1.4  8B/10B Encoder
        5. 5.3.1.5  8B/10B Decoder
        6. 5.3.1.6  64B/66B Encoder/Scrambler
        7. 5.3.1.7  64B/66B Decoder/Descrambler
        8. 5.3.1.8  Transmit Gearbox
        9. 5.3.1.9  Receive Gearbox
        10. 5.3.1.10 XAUI Lane Alignment / Code Gen (XAUI PCS)
        11. 5.3.1.11 XAUI Inter-Packet Gap (IPG) Handling
        12. 5.3.1.12 Clock Tolerance Compensation (CTC)
        13. 5.3.1.13 10GBASE-KR Auto-Negotiation
        14. 5.3.1.14 10GBASE-KR Link Training
        15. 5.3.1.15 Forward Error Correction
        16. 5.3.1.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection
        17. 5.3.1.17 10GBASE-KR Loopback Modes
        18. 5.3.1.18 10GBASE-KR Test Pattern Support
        19. 5.3.1.19 10GBASE-KR Latency
      2. 5.3.2 1GBASE-KX Mode
        1. 5.3.2.1 Sync 1 GX Block
        2. 5.3.2.2 8b/10b Encoder and Decoder Blocks
        3. 5.3.2.3 RX PCS
        4. 5.3.2.4 TX CTC
        5. 5.3.2.5 TX PCS
        6. 5.3.2.6 Test Pattern Generator
        7. 5.3.2.7 Test Pattern Verifier
        8. 5.3.2.8 1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection
        9. 5.3.2.9 1GBASE-KX Mode Latency
      3. 5.3.3 General Purpose (10G) SerDes Mode
        1. 5.3.3.1  General Purpose SERDES Transmit Data Path
        2. 5.3.3.2  General Purpose SERDES Receive Data Path
        3. 5.3.3.3  Channel Synchronization
        4. 5.3.3.4  8B/10B Encoder and Decoder
        5. 5.3.3.5  Lane Alignment Scheme for 8b/10b General Purpose Serdes Mode (Non XAUI Fata, - No /A/)
        6. 5.3.3.6  Lane Alignment Components
        7. 5.3.3.7  Lane Alignment Operation (General Purpose Serdes Mode)
        8. 5.3.3.8  Line Rate, SERDES PLL Settings, and Reference Clock Selection for the General Purpose SERDES Mode
        9. 5.3.3.9  General Purpose (10G) Loopback Modes
        10. 5.3.3.10 General Purpose (10G) Latency Measurement Function
        11. 5.3.3.11 General Purpose (10G) Mode Latency
        12. 5.3.3.12 TLK10034 Clocks: REFCLK, CLKOUT
          1. 5.3.3.12.1 General Information
        13. 5.3.3.13 TLK10034 Control Pins and Interfaces
        14. 5.3.3.14 MDIO Interface
        15. 5.3.3.15 JTAG Interface
        16. 5.3.3.16 Unused Pins
      4. 5.3.4 Provisionable XAUI Clock Tolerance Compensation
    4. 5.4 Device Functional Modes
      1. 5.4.1 Operating Modes
      2. 5.4.2 10GBASE-KR Mode
      3. 5.4.3 1GBASE-KX Mode
      4. 5.4.4 General Purpose (10G) SerDes Mode
    5. 5.5 Memory
      1. 5.5.1 Clocking Architecture (All Modes)
      2. 5.5.2 Power Down Mode
        1. 5.5.2.1 High Speed CML Output
        2. 5.5.2.2 High Speed Receiver
        3. 5.5.2.3 Loss of Signal Output Generation (LOS)
      3. 5.5.3 MDIO Management Interface
      4. 5.5.4 MDIO Protocol Timing
      5. 5.5.5 Clause 22 Indirect Addressing
      6. 5.5.6 Programmers Reference
      7. 5.5.7 Register Bit Definitions
    6. 5.6 Register Map
      1. 5.6.1 10G-KR Programmers Reference
        1. 5.6.1.1 Vendor Specific Device Registers
        2. 5.6.1.2 PMA/PMD Registers
        3. 5.6.1.3 PCS Registers
        4. 5.6.1.4 Auto-Negotiation Registers
      2. 5.6.2 1G-KX Programmers Reference
        1. 5.6.2.1 Vendor Specific Device Registers
        2. 5.6.2.2 PMA/PMD Registers
        3. 5.6.2.3 Auto-Negotiation Registers
      3. 5.6.3 10G Programmers Reference
        1. 5.6.3.1 Vendor Specific Device Registers
  6. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curve
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
          1. 6.2.4.1.1 TLK10034 High-Speed Data Path
          2. 6.2.4.1.2 AC-Coupling
          3. 6.2.4.1.3 External Clock Connections
        2. 6.2.4.2 Layout Example
        3. 6.2.4.3 Package Thermal Dissipation Ratings
    3. 6.3 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Quad-Channel Multi-Rate Transceiver
  • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet Standards
  • Supports All CPRI and OBSAI Data Rates Up to 10 Gbps
  • Supports Multi-Rate SERDES Operation with Up to 10.3125 Gbps Data Rate on the High Speed Side and Up to 5 Gbps on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP+ Optical Modules
  • Selectable Reference Clock per Channel with Multiple Output Clock Options
  • Loopback Capability on Both High Speed and Low Speed Sides
  • Supports Data Retime Operation
  • Supports PRBS, CRPAT, CJPAT, High-/Low-/Mixed-Frequency Patterns, and KR Pseudo-Random Pattern Generation and Verification, Square-Wave Generation
  • Two Power Supplies: 1.0-V, and 1.5 or 1.8-V Nominal
  • No Power Supply Sequencing Requirements
  • Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane/Cable Reach on Both High Speed and Low Speed Sides
  • Programmable Transmit Output Swing on Both High Speed and Low Speed Sides
  • Loss of Signal (LOS) Detection
  • Supports 10G-KR Link Training, Forward Error Correction, Auto-Negotiation
  • Jumbo Packet Support
  • JTAG; IEEE 1149.1/1149.6 Test Interface
  • Industry Standard MDIO Clause 45 and 22 Control Interfaces
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C)
  • Power Consumption: 825 mW per Channel (Nominal)
  • Device Package: 19-mm x 19-mm, 324-Pin PBGA, 1-mm Ball-Pitch

1.2 Applications

  • 10GBASE-KR Compliant Backplane Links
  • 10 Gigabit Ethernet Switch, Router, and Network Interface Cards
  • 10 Gigabit Ethernet Blade Servers
  • Proprietary Cable/Backplane Links
  • High-Speed Point- to-Point Transmission Systems

1.3 Description

The TLK10034 is a quad-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.

While operating in the 10GBASE-KR mode, the TLK10034 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10034 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications.

While operating in the General Purpose SERDES mode, the TLK10034 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10034 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5Gbps to 5Gbps and the high speed side data rate can range from 1Gbps to 10Gbps. 1:1 retime mode is also supported but limited to 1Gbps to 5Gbps rates.

The TLK10034 also supports 1G-KX (1.25Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioFCBGAning is used, data rates up to 3.125 Gbps are supported.

Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors.

The TLK10034 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1G-KX modes, allowing for asynchronous clocking.

The TLK10034 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes.

The TLK10034 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High, Low, Mixed, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen.

The TLK10034 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold.

In the 10GBASE-KR mode, the lane alignment for each channel is achieved through the standard XAUI lane alignment scheme. In the General Purpose SERDES mode the low speed side lane alignment for each channel is achieved through a proprietary lane alignment scheme. The upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.

The four TLK10034 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.

The low speed side of the TLK10034 is ideal for interfacing with an FPGA or ASIC capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10034 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TLK10034 FCBGA (324) 19.00 mm × 19.00 mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.

1.4 Functional Block Diagram

TLK10034 sim_1ch_bd_llsec0.gif Figure 1-1 A Simplified One Channel Block Diagram of the TLK10034 Data Paths