5.3.1.1 10GBASE-KR Transmit Data Path Overview

In 10GBASE-KR Mode, the TLK10034 takes in XAUI data on the four low speed input lanes. The serial data in each lane is deserialized into 10-bit parallel data, then byte aligned (channel synchronized) based on comma detection. The four XAUI lanes are then aligned with one another, and the aligned data is input to four 8B/10B decoders. The decoded data is then input to the transmit clock tolerance compensation (CTC) block which compensates for any frequency offsets between the incoming XAUI data and the local reference clock. The CTC block then delivers the data to a 64B/66B encoder and a scrambler. The resulting scrambled 10GBASE-KR data is then input to a transmit gearbox which in turn delivers it to the high speed side SERDES for serialization and output through the HSTX*P/N pins.

5.3.1.2 10GBASE-KR Receive Data Path Overview

In the receive direction, the TLK10034 will take in 64B/66B-encoded serial 10GBASE-KR data on the HSRX*P/N pins. This data is deserialized by a high speed SERDES, then input to a receive gearbox. After the gearbox, the data is aligned to 66-bit frames, descrambled, 64B/66B decoded, and then input to the receive CTC block. After CTC, the data is encoded by four 8B/10B encoders, and the resulting four 10-bit parallel words are serialized by the low speed SERDES blocks. The four serial XAUI output lanes are transmitted out the OUT*P/N pins.

5.3.1.3 Channel Synchronization Block

When parallel data is clocked into a parallel-to-serial converter, the byte boundary that was associated with the parallel data is lost in the serialization of the data. When the serial data is received and converted to parallel format again, a method is needed to be able to recognize the byte boundary again. Generally, this is accomplished through the use of a synchronization pattern. This is a unique pattern of 1’s and 0’s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8B/10B encoding contains a character called the comma (b’0011111’ or b’1100000’) which is used by the comma detect circuit to align the received serial data back to its original byte boundary. The TLK10034 channel synchronization block detects the comma pattern found in the K28.5 character, generating a synchronization signal aligning the data to their 10-bit boundaries for decoding. It is important to note that the comma can be either a (b’0011111’) or the inverse (b’1100000’) depending on the running disparity. The TLK10034 decoder will detect both patterns.

The TLK10034 performs channel synchronization per lane as shown in the flowchart of Figure 5-3.

Figure 5-3 Channel Synchronization Flowchart

5.3.1.4 8B/10B Encoder

Embedded-clock serial interfaces require a method of encoding to ensure sufficient transition density for the receiving CDR to acquire and maintain lock. The encoding scheme also maintains the signal DC balance by keeping the number of ones and zeros balanced which allows for AC coupled data transmission. The TLK10034 uses the 8B/10B encoding algorithm that is used by 10Gbps and 1Gbps Ethernet and Fibre Channel standards. This provides good transition density for clock recovery and improves error checking.

The 8B/10B encoder converts each 8-bit wide data to a 10-bit wide encoded data character to improve its transition density. This transmission code includes /D/ Characters, used for transmitting data, and /K/ Characters, used for transmitting protocol information. Each /K/ or /D/ character code word can also have both a positive and a negative disparity version. The disparity of a code word is selected by the encoder to balance the running disparity of the serialized data stream.

5.3.1.5 8B/10B Decoder

Once the Channel Synchronization block has identified the byte boundaries from the received serial data stream, the 8B/10B decoder converts 10-bit 8B/10B-encoded characters into their respective 8-bit formats. When a code word error or running disparity error is detected in the decoded data, the appropriate LOS pin is asserted (depending on the LOS overlay selection).

5.3.1.6 64B/66B Encoder/Scrambler

To facilitate the transmission of data received from the media access control (MAC) layer, the TLK10034 encodes data received from the MAC using the 64B/66B encoding algorithm defined in the IEEE802.3ae Clause 49.2.4 standard. The TLK10034 takes two consecutive transfers from the XAUI interface and encodes them into a 66-bit code word. The information from the two XAUI transfers includes 64 bits of data and 8 bits of control information after 8B/10B decoding.

If the 64B/66B encoder detects an invalid packet format from the XAUI interface, it replaces erroneous information with appropriately-encoded error information. The resulting 66-bit code word is then sent on to the transmit gearbox.

The encoding process implemented in the TLK10034 includes two steps:

1. an encoding step, which converts the 72 bits of data (8 data bytes plus 8 control-code indicators) received from the transmit CTC FIFO into a 66-bit code word
2. a scrambling step, which scrambles 64 bits of encoded data using the scrambler polynomial x⁵⁷+x³⁹+1. The 66 bits created by the encoder consists of 64 bits of data and a 2-bit synchronization field consisting of either 01 or 10. Only the 64 bits of data are scrambled, leaving the two synchronization bits unmodified. The two synchronization bits allow the receive gearbox to obtain frame alignment and, in addition, ensure an edge transition of at least once in 66 bits of data. The encoding process allows a limited amount of control information to be sent in-line with the data.

5.3.1.7 64B/66B Decoder/Descrambler

The data received from the serial 10GBASE-KR is 64B/66B-encoded data. The TLK10034 decodes the data received using the 64B/66B decoding algorithm defined in the IEEE 802.3-2008 Clause 49.2.4 standard. The TLK10034 creates consecutive 72-bit data words from the encoded 66-bit code words for transfer over the XAUI interface to the MAC. The information for the two XAUI transfers includes 64 bits of data and 8 bits of control information before 8B/10B encoding.

Not all 64B/66B block payloads are valid. Invalid block payloads are handled by the 64B/66B decoder block and appropriate error handling is provided, as defined in the IEEE 802.3-2008 standard. The decoding algorithm includes two steps: a descrambling step which descrambles 64 bits of the 66-bit code word with the scrambling polynomial x⁵⁷+x³⁹+1, and a decoding step which converts the 66 bits of data received into 64 bits of data and 8 bits of control information. These words are sent to the receive CTC FIFO.

5.3.1.8 Transmit Gearbox

The function of the transmit gearbox is to convert the 66-bit encoded, scrambled data stream into a 16-bit-wide data stream to be sent out to the serializer and ultimately to the physical medium attachment (PMA) device. The gearbox is needed because while the effective bit rate of the 66-bit data stream is equal to the effective bit rate of the 16-bit data, the clock rates of the two buses are of different frequencies.

5.3.1.9 Receive Gearbox

While the transmit gearbox only performs the task of converting 66-bit data to be transported on to the 16-bit serializer, the receive gearbox has more to do than just the reverse of this function. The receive gearbox must also determine where within the incoming data stream the boundaries of the 66-bit code words are.

The receive gearbox has the responsibility of initially synchronizing the header field of the code words and continuously monitoring the ongoing synchronization. After obtaining synchronization to the incoming data stream, the gearbox assembles 66-bit code words and presents these to the 64B/66B decoder.

Note that in FEC mode, the Receive Gearbox blindly converts 16-bit data to 66-bit data and depends on the RX FEC logic to frame align the data.

5.3.1.10 XAUI Lane Alignment / Code Gen (XAUI PCS)

The XAUI interface standard is defined to allow for 21 UI of skew between lanes. This block is implemented to handle up to 30 UI (XAUI UI) of skew between lanes using /A/ characters. The state machine follows the standard 802.3-2008 defined state machine.

5.3.1.11 XAUI Inter-Packet Gap (IPG) Handling

The XAUI interface transports information that consists of packets and inter-packet gap (IPG) characters. The IEEE 802.3ae standard defines that the IPG, when transferred over the XAUI interface, consists of alignment characters (/A/), control characters (/K/) and replacement characters (/R/).

TLK10034 converts all AKR characters to IDLE characters, performs insertions or deletions on the IDLE characters, and transmits only encoded IDLE characters out to the 10GBASE-KR interface. The receive channel expects encoded IDLE characters to enter the 10GBASE-KR interface, and performs insertions and deletions on IDLE characters and then converts IDLE characters back to AKR characters. Any AKR characters received on the high speed interface are by default converted to IDLE characters for reconversion to AKR columns.

Both the transmit and receive FIFOs rely upon a valid IDLE stream to perform clock tolerance compensation (CTC).

5.3.1.12 Clock Tolerance Compensation (CTC)

The XAUI interface is defined to allow for separate clock domains on each side of the link. Though the reference clocks for two devices on a XAUI link have the same specified frequencies, there are slight differences that, if not compensated for, will lead to over or under run of the FIFO’s on the receive/transmit data path. The TLK10034 provides compensation for these differences in clock frequencies via the insertion or the removal of idle (/I/) characters on all lanes, as shown in Figure 5-4 and
Figure 5-5.

Figure 5-4 Clock Tolerance Compensation: Add

The /R/ code is disparity neutral, allowing its removal or insertion without affecting the current running disparity of each channel’s serial stream.

Figure 5-5 Clock Tolerance Compensation: Drop

The TLK10034 allows for provisioning of both the CTC FIFO depth and the low/high watermark thresholds that trigger idle insertion/deletion beyond the standard requirements. This allows for optimization between maximum clock tolerance and packet length. For more information on the TLK10034 CTC provisioning, see Appendix A.

5.3.1.13 10GBASE-KR Auto-Negotiation

When TLK10034 is selected to operate in 10GKR/1G-KX mode (MODE_SEL pin held low), Clause 73 Auto-Negotiation will commence after power up or hardware or software reset. The data path chosen from the result of Auto-Negotiation will be the highest speed of 10G-KR or 1G-KX as advertised in the MDIO ability fields (set to 10G-KR by default). If 10G-KR is chosen, link training will commence immediately following the completion of Auto-Negotiation. Legacy devices that operate in 1G-KX mode and do not support Clause 73 Auto Negotiation will be recognized through the Clause 73 parallel detect mechanism.

5.3.1.14 10GBASE-KR Link Training

Link training for 10G-KR mode is performed after auto-negotiation, and follows the procedure described in IEEE 802.3-2008. The high speed TX SERDES side will update pre-emphasis tap coefficients as requested through the Coefficient update field. Received training patterns are monitored for bit errors (MDIO configurable), and requests are made to update partner channel TX coefficients until optimal settings are achieved.

The RX link training algorithm consists of sending a series of requests to move the link partner’s transmitter tap coefficients to the center point of an error free region. Once link training has completed, the 10G-KR data path is enabled. If link is lost, the entire process repeats with auto-negotiation, link training, and 10G-KR mode.

5.3.1.15 Forward Error Correction

Optionally enabled, Forward Error Correction (FEC) follows the IEEE 802.3-2008 standard, and is able to correct a burst errors up to 11 bits. In the TX data path, the FEC logic resides between the scrambler and gearbox. In the RX datapath, FEC resides between the gearbox and descrambler. Frame alignment is handled inside the RX FEC block during FEC operation, and the RX gearbox sync header alignment is bypassed. Because latency is increased in both the TX and RX data paths with FEC enabled, it is disabled by default and must be enabled through MDIO programming. Note that FEC by nature will add latency due to frame storage.

5.3.1.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection

The TLK10034 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers are available for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies for various applications.

The external differential reference clock has a large operating frequency range allowing support for many different applications. The reference clock frequency must be within ±200 PPM of the incoming serial data rate (±100 PPM of nominal data rate), and have less than the specified jitter characteristics (see Section 4.10).

When the TLK10034 device is set to operate in the 10GBASE-KR mode with a low speed side line rate of 3.125Gbps and a high speed side line rate of 10.3125Gbps, the reference clock choices are as shown in Table 5-1.

5.3.1.17 10GBASE-KR Loopback Modes

In 10G-KR mode, the TLK10034 supports looping back of data on both the XAUI (local) side and 10G-KR (remote) side. In either case, the loopback point can be chosed to be either prior to serialization (shallow) or after serialization (deep). The various loopback modes can be activated and configured via MDIO register settings.

The datapath for deep remote loopback is shown in Figure 5-6. The data is accepted on the high speed side receive SERDES pins (HSRX*P/N), traverses the entire receive data path is returned through the entire transmit data path and sent out through the high speed side transmit SERDES pins (HSTX*P/N). The low speed side outputs on OUT*P/N pins are still available for monitoring and should be correctly terminated. The low speed side inputs on IN*P/N should be electrically idle (floating).

Figure 5-6 Deep Remote Loopback for the 10GBASE-KR Mode

Note that in deep remote loopback mode, the the LS serial transmitter is internally connected directly to the LS serial receiver. This short, low-loss interconnect will have different properties than a typical PCB interconnect, so different transmit and receive link settings should be used to optimize BER.

The datapath for shallow remote loopback is shown in Figure 5-7. In this mode, the device functions as a high speed serial retimer. The data is accepted on the high speed side receive SERDES pins (HSRX*P/N), traverses the receive data path through the RX CTC block, is looped back before the 8B/10B encoders, and is returned through the transmit data path to be sent out through the high speed side transmit SERDES pins (HSTX*P/N).

The low speed side transmit path SERDES can be optionally enabled or disabled, but the PLL needs to be enabled to provide the required clock. The low speed side outputs on OUTA*P/N pins are available for monitoring and must be correctly terminated.

Figure 5-7 Shallow Remote Loopback (Serial Retime) for the 10GBASE-KR Mode

The datapath for deep local loopback is shown in Figure 5-8. The data is accepted on the low speed side SERDES pins (IN*P/N), traverses the entire transmit data path, is returned through the entire receive data path and sent out through the low speed side receive SERDES pins (OUT*P/N). The high speed side outputs on HSTX*P/N pins are available for monitoring. The high speed side inputs on HSRX*P/N should be electrically idle (floating).

Figure 5-8 Deep Local Loopback for the 10GBASE-KR Mode

Note that in deep local loopback mode, the HS serial transmitter is internally connected directly to the HS serial receiver. This short, low-loss interconnect will have different properties than a typical PCB interconnect, so different transmit and receive link settings should be used to optimize BER.

The datapath for shallow local loopback is shown in Figure 5-9. The data is accepted on the low speed side SERDES pins (IN*P/N), traverses the transmit data path up to the HS SERDES, is looped back before through the receive data path, and sent out through the low speed side receive SERDES pins (OUT*P/N). The high speed side outputs on HSRX*P/N pins are available for monitoring.

Figure 5-9 Shallow Local Loopback for the 10GBASE-KR Mode

5.3.1.18 10GBASE-KR Test Pattern Support

The TLK10034 has the capability to generate and verify various test patterns for self-test and system diagnostic measurements. The following test patterns are supported:

• High Speed (HS) Side: PRBS 2⁷ – 1, PRBS 2²³ – 1, PRBS 2³¹ – 1, Square Wave with Provisionable Length, and KR Pseudo-Random Pattern
• Low Speed (LS) Side: PRBS 2⁷ – 1, PRBS 2²³ – 1, PRBS 2³¹ – 1, High Frequency, Low Frequency, Mixed Frequency, CRPAT, CJPAT.

The TLK10034 provides two pins: PRBSEN and PRBS_PASS, for additional control and monitoring of PRBS pattern generation and verification. When the PRBSEN is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides of all channels. PRBS 2³¹-1 is selected by default, and can be changed through MDIO.

When PRBS test is enabled (PRBSEN=1):

• PRBS_PASS = 1 indicates that PRBS pattern reception is error free.
• PRBS_PASS = 0 indicates that a PRBS error is detected. The channel, the side (high speed or low speed), and the lane (for low speed side) that this signal refers to is chosen through MDIO.

For further details, refer to the application note TLK10034 Test Pattern Procedures.

5.3.1.19 10GBASE-KR Latency

The latency through the TLK10034 in 10GBASE-KR mode is as shown in Figure 5-10. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed.

Figure 5-10 10GBASE-KR Mode Latency Per Block

5.3.2.1 Sync 1 GX Block

This block is used to align the deserialized signals to the proper 10-bit word boundaries. The Sync 1 GX block generates a synchronization flag indicating incoming data is synchronized to the correct bit boundary. This module implements the synchronization state machine found in Figure 36-9 of the IEEE 802.3-2008 Standard. A synchronization status signal, latched low, is available to indicate synchronization errors.

5.3.2.2 8b/10b Encoder and Decoder Blocks

As in the 10GBASE-KR operating mode, these blocks are used to convert between 10-bit (encoded) data and 8-bit data words. They can be optionally bypassed. A code invalid signal, latched low, is available to indicate 8b/10b encode and decode errors.

5.3.2.3 RX PCS

This block implements the PCS receive function for Gigabit Ethernet mode as defined in Clause 36. It operates on decoded characters. This block can also be bypassed.

5.3.2.4 TX CTC

The transmit clock tolerance compensation (CTC) block acts as a FIFO with add and delete capabilities, adding and deleting 2 cycles each time to support ±200ppm during IFG (no errors) between the read and write clocks. This block implements a 12 deep asynchronous FIFO with a usable space 8 deep. It has two separate pointer tracking systems. One determines when to delete or insert and another determines when to reset. Inserts and deletes are only allowed during non-errored inter-frame gaps and occurs 2 cycles at a time. It has an auto reset feature once collision occurs. If a collision occurs, the indication is latched high until read by MDIO.

5.3.2.5 TX PCS

The TX PCS block implements the PCS Transmit ordered_set and transmit code_group FSMs as specified in Clause 36. This block can be bypassed.

5.3.2.6 Test Pattern Generator

In 1G-KX mode, this block can be used to generate test patterns allowing the 1G-KX channel to be tested for compliance while in a system environment or for diagnostic purposes. Test patterns generated are high/low/mixed frequency and CRPAT long or short.

5.3.2.7 Test Pattern Verifier

The 1G-KX test pattern verifier performs the verification and error reporting for the CRPAT Long and Short test patterns specified in Annex 36A of the IEEE 802.3-2002 standard. Errors are reported to MDIO registers.

5.3.2.8 1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection

When the TLK10034 is configured to operate in the 1GBASE-KX mode, the available line rates, reference clock frequencies, and corresponding PLL multipliers are summarized in Table 5-2.

5.3.2.9 1GBASE-KX Mode Latency

The latency through the TLK10034 in 1G-KX mode is as shown in Figure 5-11. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed.

Figure 5-11 1G-KX Mode Latency

5.3.3.1 General Purpose SERDES Transmit Data Path

The TLK10034 General Purpose SERDES low speed to high speed (transmit) data path with the device configured to operate in the normal transceiver (mission) mode is shown in the upper half of Figure 5-33. In this mode, 8B/10B encoded serial data (IN*P/N) in 2 or 4 lanes is received by the low speed side SERDES and deserialized into 10-bit parallel data for each lane. The data in each individual lane is then byte aligned (channel synchronized) and then 8B/10B decoded into 8-bit parallel data for each lane. The lane data is then lane aligned by the Lane Alignment Slave. 32-bits of lane aligned parallel data is subsequently fed into a transmit FIFO which delivers it to an 8B/10B encoder, 16 data bits at a time. The resulting 20-bit 8B/10B encoded parallel data is sent to the high speed side SERDES for serialization and output through the HSTX*P/N pins.

5.3.3.2 General Purpose SERDES Receive Data Path

With the device configured to operate in the normal transceiver (mission) mode, the high speed to low speed (receive) data path is shown in the lower half of Figure 5-33. 8B/10B encoded serial data (HSRX*P/N) is received by the high speed side SERDES and deserialized into 20-bit parallel data. The data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and then delivered to a receive FIFO. The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment Master which splits the data into the same number of lanes as configured on the transmit data path. The lane data is then 8B/10B encoded and the resulting 10-bit parallel data for each lane is fed into the low speed side SERDES for serialization and output through the OUT*P/N pins. This process is exactly the same for all the channels (A, B, C, and D).

5.3.3.3 Channel Synchronization

As in the 10GBASE-KR mode, the channel synchronization block is used in the 10G General Purpose SERDES mode to align received serial data to a defined byte boundary. The channel synchronization block detects the comma pattern found in the K28.5 character, and follows the synchronization flowchart shown in Figure 5-3.

5.3.3.4 8B/10B Encoder and Decoder

As in the 10GBASE-KR and 1GBASE-KX modes, the 8B/10B encoder and decoder blocks are used to convert between 10-bit (encoded) and 8-bit (unencoded) data words.

5.3.3.5 Lane Alignment Scheme for 8b/10b General Purpose Serdes Mode (Non XAUI Fata, - No /A/)

Lower rate multi-lane serial signals per channel must be byte aligned and lane aligned such that high speed multiplexing (proper reconstruction of higher rate signal) is possible. For that reason, the TLK10034 implements a special lane alignment scheme on the low speed (LS) side for 8b/10b data that does not contain XAUI alignment characters.

During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate byte boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original higher rate data ordering is restored.

Lane alignment completes successfully when the LS receiver asserts a “Link Status OK” signal monitored by the LS transmitter on the link partner device such as an FPGA. The TLK10034 sends out the “Link Status OK” signals through the LS_OK_OUT_A/B/C/D output pins, and monitors the “Link Status OK” signals from the link partner device through the LS_OK_IN_A/B/C/D input pins. If the link partner device does not need the TLK10034 LAM to send proprietary lane alignment pattern, LS_OK_IN_A/B/C/D can be tied high on the application board or set through MDIO register bits.

The lane alignment scheme is activated under any of the following conditions:

• Device/System power up (after configuration/provisioning)
• Loss of channel synchronization assertion on any enabled LS lane
• Loss of signal assertion on any enabled LS lane
• LS SERDES PLL Lock indication deassertion
• After software determined LS 8B/10B decoder error rate threshold exceeded
• After device reset is deasserted
• Any time the LS receiver deasserts “Link Status OK”.
• Presence of reoccurring higher level / protocol framing errors

All the above conditions are selectable through MDIO register provisioning.

The block diagram of the lane alignment scheme is shown in Figure 5-12.

Figure 5-12 Block Diagram of the Lane Alignment Scheme

5.3.3.6 Lane Alignment Components

• Lane Alignment Master (LAM)
  • Responsible for generating proprietary LS lane alignment initialization pattern
  • Resides in the TLK10034 receive path (one instance per channel)
    • Responsible for bringing up LS receive link for the data sent from the TLK10034 to a link partner device
    • Monitors the LS_OK_IN pins for Link Status OK signals sent from the Lane Alignment Slave (LAS) of the link partner device
  • Resides in the link partner device (one instance per channel)
    • Responsible for bringing up LS transmit link for the data sent from the link partner device to the TLK10034
    • Monitors the Link Status OK signals sent from the LS_OK_OUT pins of the Lane Alignment Slave (LAS) of the TLK10034
• Lane Alignment Slave (LAS)
  • Responsible for monitoring the LS lane alignment initialization pattern
  • Performs channel synchronization per lane (2 or 4 lanes) through byte rotation
  • Performs lane alignment and realignment of bytes across lanes
  • Resides in the TLK10034 transmit path (one instance per channel)
    • Generates the Link Status OK signal for the LAM on the link partner device
  • Resides in the link partner device (one instance per channel)
    • Generates the Link Status OK signal for the LAM on the TLK10034 device.

5.3.3.7 Lane Alignment Operation (General Purpose Serdes Mode)

During lane alignment, the LAM sends a repeating pattern of 49 characters (control + data) simultaneously across all enabled LS lanes. These simultaneous streams are then encoded by 8B/10B encoders in parallel. The proprietary lane alignment pattern consists of the following characters:

/K28.5/ (CTL=1, Data=0xBC)

Repeat the following sequence of 12 characters four times:

/D30.5/ (CTL=0, Data=0xBE)
/D23.6/ (CTL=0, Data=0xD7)
/D3.1/ (CTL=0, Data=0x23)
/D7.2/ (CTL=0, Data=0x47)
/D11.3/ (CTL=0, Data=0x6B)
/D15.4/ (CTL=0, Data=0x8F)
/D19.5/ (CTL=0, Data=0xB3)
/D20.0/ (CTL=0, Data=0x14)
/D30.2/ (CTL=0, Data=0x5E)
/D27.7/ (CTL=0, Data=0xFB)
/D21.1/ (CTL=0, Data=0x35)
/D25.2/ (CTL=0, Data=0x59)

The above 49-character sequence is repeated until LS_OK_IN is asserted. Once LS_OK_IN is asserted, the LAM resumes transmitting traffic received from the high speed side SERDES immediately.

The TLK10034 performs lane alignment across the lanes similar in fashion to the IEEE 802.3-2008 (XAUI) specification. XAUI only operates across 4 lanes while LAS operates with 2 or 4 lanes. The lane alignment state machine is shown in Figure 5-13. The TLK10034 uses the comma (K28.5) character for lane to lane alignment by default, but can be provisioned to use XAUI's /A/ character as well.

Lane alignment checking is not performed by the LAS after lane alignment is achieved. After LAM detects that the LS_OK_IN signal is asserted, normal system traffic is carried instead of the proprietary lane alignment pattern.

Channel synchronization is performed during lane alignment and normal system operation.

Figure 5-13 Lane Alignment State Machine

5.3.3.8 Line Rate, SERDES PLL Settings, and Reference Clock Selection for the General Purpose SERDES Mode

When the TLK10034 is set to operate in the General Purpose SERDES mode, the following tables show a summary of line rates and reference clock frequencies used for CPRI/OBSAI for 1:1, 2:1 and 4:1 operation modes.

Table 5-3, Table 5-4, and Table 5-5 indicate two possible reference clock frequencies for CPRI/OBSAI applications: 153.6MHz and 122.88MHz, which can be used based on the application preference. The SERDES PLL Multiplier (MPY) has been given for each reference clock frequency respectively. For each channel, the low speed side and the high speed side SERDES use the same reference clock frequency. Note that Channel A, B, C and D are independent and their application rates and references clocks are separate.

For other line rates not shown in Table 5-3, Table 5-4, or Table 5-5, valid reference clock frequencies can be selected with the help of the information provided in Table 5-6 and Table 5-7 for the low speed and high speed side SERDES. The reference clock frequency has to be the same for the two SERDES and must be within the specified valid ranges for different PLL multipliers.

For example, in the 2:1 operation mode, if the low speed side line rate is 1.987Gbps, the high-speed side line rate will be 3.974Gbps. The following steps can be taken to make a reference clock frequency selection:

1. Determine the appropriate SERDES rate modes that support the required line rates. Table 5-6 shows that the 1.987Gbps line rate on the low speed side is only supported in the half rate mode (RateScale = 1). Table 5-7 shows that the 3.974Gbps line rate on the high speed side is only supported in the half rate mode (RateScale = 1).
2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding reference clock frequencies using the formula:

Reference Clock Frequency = (LineRate x RateScale)/MPY

The computed reference clock frequencies are shown in Table 5-8 along with the valid minimum and maximum frequency values.

3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that fall outside the allowed range. In this example, the common frequencies are highlighted in Table 5-8. The highest and lowest computed reference clock frequencies must be discarded because they exceed the recommended range.
4. Select any of the remaining marked common reference clock frequencies. Higher reference clock frequencies are generally preferred. In this example, any of the following reference clock frequencies can be selected: 397.4MHz, 331.167MHz, 248.375MHz, 198.7MHz, 165.583MHz, 158.96MHz, and 132.467MHz

5.3.3.9 General Purpose (10G) Loopback Modes

In General Purpose (10G) mode, the TLK10034 supports looping back of data on both the LS (local) side and HS (remote) side. The loopback point can be chosen to be either prior to serialization (shallow) or after serialization (deep). The various loopback modes can be activated and configured through the MDIO interface.

The datapath for deep remote loopback mode is shown in Figure 5-14. The data is accepted on the high speed side receive SERDES pins (HSRX*P/N), traverses the entire receive data path, is returned through the entire transmit data path and sent out through the high speed side transmit SERDES pins (HSTX*P/N). The low speed side outputs on OUT*P/N pins are still available for monitoring and should be correctly terminated. The low speed side inputs on IN*P/N should be electrically idle (floating).

Figure 5-14 Deep Remote Loopback for the General Purpose SERDES Mode

Note that in deep remote loopback mode, the the LS serial transmitter is internally connected directly to the LS serial receiver. This short, low-loss interconnect will have different properties than a typical PCB interconnect, so different transmit and receive link settings should be used to optimize BER.

The datapath for shallow remote loopback mode is shown in Figure 5-15. In this mode, the device functions as a high speed serial retimer. The data is accepted on the high speed side receive SERDES pins (HSRX*P/N), traverses the receive data path up to the LS SERDES, and is looped back through the transmit data path to be sent out through the high speed side transmit SERDES pins (HSTX*P/N).

In shallow remote loopback mode, the low speed side transmit path SERDES can be optionally enabled or disabled, but the PLL needs to be enabled to provide the required clock. The low speed side outputs on OUTA*P/N pins are available for monitoring and must be correctly terminated. The internal LAS’s link status is automatically routed to the LAM so that lane alignment can take place.

Figure 5-15 Shallow Remote Loopback for the General Purpose SERDES Mode

The datapath for deep local loopback mode is shown in Figure 5-16. Data is accepted on the low speed side SERDES pins (IN*P/N), traverses the entire transmit data path, is returned through the entire receive data path to be sent out through the low speed side receive SERDES pins (OUT*P/N). Note that lane alignment still must occur before passing traffic. The high speed side outputs on the HSTX*P/N pins are available for monitoring. The high speed side inputs on HSRX*P/N should be electrically idle (floating).

Figure 5-16 Deep Local Loopback for the General Purpose SERDES Mode

Note that in deep local loopback mode, the the HS serial transmitter is internally connected directly to the HS serial receiver. This short, low-loss interconnect will have different properties than a typical PCB interconnect, so different transmit and receive link settings should be used to optimize BER.

In shallow local loopback mode, the data is accepted on the low speed side SERDES pins (IN*P/N), traverses the transmit data path up to the HS SERDES, is looped back before through the receive data path, and sent out through the low speed side receive SERDES pins (OUT*P/N). The high speed side outputs on HSRX*P/N pins are available for monitoring.

5.3.3.10 General Purpose (10G) Latency Measurement Function

The TLK10034 includes a latency measurement function to support CPRI and OBSAI type applications. There are two start and two stop locations for the latency counter as shown in Figure 5-17 for Channel A. The start and stop locations are selectable through MDIO register bits. The elapsed time from a comma detected at an assigned counter start location of a particular channel to a comma detected at an assigned counter stop location of the same channel is measured and reported through the MDIO interface. The function may operate independently on each channel. The following three control characters (containing commas) are monitored:

1. K28.1 (control = 1, data = 0x3C)
2. K28.5 (control = 1, data = 0xBC)
3. K28.7 (control = 1, data = 0xFC).

The first comma found at the assigned counter start location will start up the latency counter. The first comma detected at the assigned counter stop location will stop the latency counter. The 20-bit latency counter result of this measurement is readable through the MDIO interface. The accuracy of the measurement is a function of the serial bit rate at which the channel being measured is operating. The register will return a value of 0xFFFFF if the duration between transmit and receive comma detection exceeds the depth of the counter. Only one measurement value is stored internally until the 20-bit results counter is read. The counter will return zero in cases where a transmit comma was never detected (indicating the results counter never began counting).

It is also possible to start and stop the counter using the PRTAD1 pin. This allows the stopwatch circuit to be triggered from an external device such as the low speed side link partner.

For a detailed description of the latency measurement procedure, please refer to the application note TLK10034 Latency Measurement Function.

Figure 5-17 Location of TX and RX Comma Character Detection (Only Channel A Shown)

In high speed side SERDES full rate mode, the latency measurement function runs off of an internal clock which is equal to the frequency of the transmit serial bit rate divided by 8. In half rate mode, the latency measurement function runs off of an internal clock which is equal to the serial bit rate divided by 4. In quarter rate mode, the latency measurement function runs off of an internal clock which is equal to the serial bit rate divided by 2. In eighth rate mode, the latency measurement function runs off of a clock which is equal to the serial bit rate.

The latency measurement does not include the low speed side transmit SERDES contribution as well as part of the channel synchronization block. The latency introduced by those two is up to (18 + 10) x N high speed side unit intervals (UIs), where N = 2, 4 is the multiplex factor. The latency measurement also doesn’t account for the low speed side receive SERDES contribution which is estimated to be up to 20 x N high speed side UIs.

The latency measurement accuracy in all cases is equal to plus or minus one latency measurement clock period. The measurement clock can be divided down if a longer duration measurement is required, in which case the accuracy of the measurement is accordingly reduced. The high speed latency measurement clock is divided by either 1, 2, 4, or 8 via register settings. The measurement clock used is always selected by the channel under test. The high speed latency measurement clock may only be used when operating at one of the serial rates specified in the CPRI/OBSAI specifications. It is also possible to run the latency measurement function off of the recovered byte clock for the channel under test (giving a latency measurement clock frequency equal to the serial bit rate divided by 20).

The accuracy for the standard based CPRI/OBSAI application rates is shown in Table 5-9, and assumes the latency measurement clock is not divided down per user selection (division is required to measure a duration greater than 682us). For each division of 2 in the measurement clock, the accuracy is also reduced by a factor of two.

5.3.3.11 General Purpose (10G) Mode Latency

The latency through the TLK10034 in general purpose (10G) mode is as shown in Figure 5-18. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed.

Figure 5-18 General Purpose Mode Latency

5.3.3.12 TLK10034 Clocks: REFCLK, CLKOUT

5.3.3.13 TLK10034 Control Pins and Interfaces

The TLK10034 device features a number of control pins and interfaces, some of which are described below.

5.3.3.14 MDIO Interface

The TLK10034 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the serial links.

The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference (MDC). The port address is determined by the PRTAD[4:0] control pins.

The MDIO pin requires a pullup to VDDO[1:0]. No pullup is needed on the MDC pin if driven with a push-pull MDIO master, but a pullup to VDDO[1:0] is needed if driven with an open-drain MDIO master.

5.3.3.15 JTAG Interface

The JTAG interface is mostly used for device test. The JTAG interface operates through the TDI, TDO, TMS, TCK, and TRST_N pins. If not used, all the pins can be left unconnected except TDI and TCK which have to be grounded.

5.3.3.16 Unused Pins

As a general guideline, any unused LVCMOS input pin needs to be grounded and any unused LVCMOS output pin can be left unconnected. Unused CML differential output pins can be left unconnected. Unused CML differential input pins should be tied to ground through a shared 100-Ω resistor.

Table 5-12 XAUI CTC FIFO Configurations

Table 5-13 TLK10034 Operating Mode Selection

Table 5-14 HSRX*_CLKOUTP/N Power Down Settings⁽¹⁾

Table 5-15 LS0_CLKOUTP/N Power Down Settings

Table 5-16 LS1_CLKOUTP/N Power Down Settings

Table 5-17 HSTX0_CLKOUTP/N Power Down Settings

Table 5-18 HSTX1_CLKOUTP/N Power Down Settings

5.5.2.1 High Speed CML Output

The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up resistors, requiring no external components. The transmit outputs must be AC coupled.

NOTE:

Channel A HS Side is Shown

Figure 5-36 Example of High Speed I/O AC Coupled Mode

Current Mode Logic (CML) drivers often require external components. The disadvantage of the external component is a limited edge rate due to package and line parasitic. The CML driver on TLK10034 has on-chip 50Ω termination resistors terminated to VDDT, providing optimum performance for increased speed requirements. The transmitter output driver is highly configurable allowing output amplitude and de-emphasis to be tuned to a channel's individual requirements. Software programmability allows for very flexible output amplitude control. Only AC coupled output mode is supported.

When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal is attenuated due to the skin effect of the media. This causes a “smearing” of the data eye when viewed on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to provide equalization for the high frequency loss, 3-tap finite impulse response (FIR) transmit de-emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. Output swing control is via MDIO.

See Figure 4-2 for output waveform flexibility. The level of de-emphasis is programmable via the MDIO interface through control registers through pre-cursor and post-cursor settings. Users can control the strength of the de-emphasis to optimize for a specific system requirement.

5.5.2.2 High Speed Receiver

The high speed receiver is differential CML with internal termination resistors. The receiver requires AC coupling. The termination impedances of the receivers are configured as 100 Ω with the center tap weakly tied to 0.7×VDDT with a capacitor to create an AC ground (see Figure 5-36).

TLK10034 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion loss by amplifying the high frequency components of the signal, reducing inter-symbol interference. Equalization can be enabled or disabled per register settings.

5.5.2.3 Loss of Signal Output Generation (LOS)

Loss of input signal detection is based on the voltage level of each serial input signal IN*P/N, HSRX*P/N. When LOS indication is enabled and a channel’s differential serial receive input level is < 65 mVpp, that channel’s respective LOS indicator will be asserted (high true). If the input signal is > 175 mVpp, the LOS indicator will be deasserted (low false). Outside of these ranges, the LOS indication is undefined. The LOS indications are also directly readable through the MDIO interface in respective registers.

The following additional critical status conditions can be combined with the loss of signal condition enabling additional real-time status signal visibility on the LOS* outputs per channel:

1. Loss of Channel Synchronization Status – Logically OR’d with LOS condition(s) when enabled. Loss of channel synchronization can be optionally logically OR’d (disabled by default) with the internally generated LOS condition (per channel).
2. Loss of PLL Lock Status on LS and HS sides – Logically OR’d with LOS condition(s) when enabled. The internal PLL loss of lock status bit is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
3. Receive 8B/10B Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR’d with LOS condition(s) when enabled. The occurrence of an 8B/10B decode error (invalid code word or disparity error) is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
4. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR’d with LOS condition(s) when enabled. HS RX SERDES adaptive gain control unlocked indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
5. AZDONE (Auto Zero Calibration Done) - Inverted and Logically OR’d with LOS conditions(s) when enabled. HS RX SERDES auto-zero not done indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).

Refer to Figure 5-37, which shows the detailed implementation of the LOSA signal along with the associated MDIO control registers for the General Purpose SERDES mode. More details about LOS settings including configurations related to the 10GBASE-KR mode can be found in the Programmers Reference section.

Figure 5-37 LOSA – Logic Circuit Implementation

Table 5-19 Mode Selection

5.6.1.1 Vendor Specific Device Registers

These registers can be accessed by setting device address field to 0x1E (DA[4:0] = 5’b11110).

The registers below can be accessed directly through Clause 45. Contains mode specific control/status registers and implemented per channel basis.

The registers below can be accessed directly through Clause 45. Contains device specific debug control/status registers and not implemented per channel basis (i.e. same physical register accessed irrespective of channel addressed).

5.6.1.2 PMA/PMD Registers

The registers below can be accessed only in Clause 45 mode and with device address field set to 0x01 (DA[4:0] = 5’b00001).

5.6.1.3 PCS Registers

The registers below can be accessed only in Clause 45 mode and with device address field set to 0x03 (DEVADD [4:0] = 5’b00011). Valid only when device is in 10GBASE-KR mode.