SLLSEC7A August   2012  – October 2015 TLK10034

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  LVCMOS Electrical Characteristics (VDDO)
    6. 4.6  High Speed Side Serial Transmitter Characteristics
    7. 4.7  High Speed Side Serial Receiver Characteristics
    8. 4.8  Low Speed Side Serial Transmitter Characteristics
    9. 4.9  Low Speed Side Serial Receiver Characteristics
    10. 4.10 Reference Clock Characteristics (REFCLK0P/N, REFCLK1P/N)
    11. 4.11 Differential Output Clock Characteristics (CLKOUTA/B/C/DP/N)
    12. 4.12 MDIO Timing Requirements
    13. 4.13 JTAG Timing Requirements
    14. 4.14 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagrams
    3. 5.3 Feature Description
      1. 5.3.1 10GBASE-KR Mode
        1. 5.3.1.1  10GBASE-KR Transmit Data Path Overview
        2. 5.3.1.2  10GBASE-KR Receive Data Path Overview
        3. 5.3.1.3  Channel Synchronization Block
        4. 5.3.1.4  8B/10B Encoder
        5. 5.3.1.5  8B/10B Decoder
        6. 5.3.1.6  64B/66B Encoder/Scrambler
        7. 5.3.1.7  64B/66B Decoder/Descrambler
        8. 5.3.1.8  Transmit Gearbox
        9. 5.3.1.9  Receive Gearbox
        10. 5.3.1.10 XAUI Lane Alignment / Code Gen (XAUI PCS)
        11. 5.3.1.11 XAUI Inter-Packet Gap (IPG) Handling
        12. 5.3.1.12 Clock Tolerance Compensation (CTC)
        13. 5.3.1.13 10GBASE-KR Auto-Negotiation
        14. 5.3.1.14 10GBASE-KR Link Training
        15. 5.3.1.15 Forward Error Correction
        16. 5.3.1.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection
        17. 5.3.1.17 10GBASE-KR Loopback Modes
        18. 5.3.1.18 10GBASE-KR Test Pattern Support
        19. 5.3.1.19 10GBASE-KR Latency
      2. 5.3.2 1GBASE-KX Mode
        1. 5.3.2.1 Sync 1 GX Block
        2. 5.3.2.2 8b/10b Encoder and Decoder Blocks
        3. 5.3.2.3 RX PCS
        4. 5.3.2.4 TX CTC
        5. 5.3.2.5 TX PCS
        6. 5.3.2.6 Test Pattern Generator
        7. 5.3.2.7 Test Pattern Verifier
        8. 5.3.2.8 1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection
        9. 5.3.2.9 1GBASE-KX Mode Latency
      3. 5.3.3 General Purpose (10G) SerDes Mode
        1. 5.3.3.1  General Purpose SERDES Transmit Data Path
        2. 5.3.3.2  General Purpose SERDES Receive Data Path
        3. 5.3.3.3  Channel Synchronization
        4. 5.3.3.4  8B/10B Encoder and Decoder
        5. 5.3.3.5  Lane Alignment Scheme for 8b/10b General Purpose Serdes Mode (Non XAUI Fata, - No /A/)
        6. 5.3.3.6  Lane Alignment Components
        7. 5.3.3.7  Lane Alignment Operation (General Purpose Serdes Mode)
        8. 5.3.3.8  Line Rate, SERDES PLL Settings, and Reference Clock Selection for the General Purpose SERDES Mode
        9. 5.3.3.9  General Purpose (10G) Loopback Modes
        10. 5.3.3.10 General Purpose (10G) Latency Measurement Function
        11. 5.3.3.11 General Purpose (10G) Mode Latency
        12. 5.3.3.12 TLK10034 Clocks: REFCLK, CLKOUT
          1. 5.3.3.12.1 General Information
        13. 5.3.3.13 TLK10034 Control Pins and Interfaces
        14. 5.3.3.14 MDIO Interface
        15. 5.3.3.15 JTAG Interface
        16. 5.3.3.16 Unused Pins
      4. 5.3.4 Provisionable XAUI Clock Tolerance Compensation
    4. 5.4 Device Functional Modes
      1. 5.4.1 Operating Modes
      2. 5.4.2 10GBASE-KR Mode
      3. 5.4.3 1GBASE-KX Mode
      4. 5.4.4 General Purpose (10G) SerDes Mode
    5. 5.5 Memory
      1. 5.5.1 Clocking Architecture (All Modes)
      2. 5.5.2 Power Down Mode
        1. 5.5.2.1 High Speed CML Output
        2. 5.5.2.2 High Speed Receiver
        3. 5.5.2.3 Loss of Signal Output Generation (LOS)
      3. 5.5.3 MDIO Management Interface
      4. 5.5.4 MDIO Protocol Timing
      5. 5.5.5 Clause 22 Indirect Addressing
      6. 5.5.6 Programmers Reference
      7. 5.5.7 Register Bit Definitions
    6. 5.6 Register Map
      1. 5.6.1 10G-KR Programmers Reference
        1. 5.6.1.1 Vendor Specific Device Registers
        2. 5.6.1.2 PMA/PMD Registers
        3. 5.6.1.3 PCS Registers
        4. 5.6.1.4 Auto-Negotiation Registers
      2. 5.6.2 1G-KX Programmers Reference
        1. 5.6.2.1 Vendor Specific Device Registers
        2. 5.6.2.2 PMA/PMD Registers
        3. 5.6.2.3 Auto-Negotiation Registers
      3. 5.6.3 10G Programmers Reference
        1. 5.6.3.1 Vendor Specific Device Registers
  6. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curve
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
          1. 6.2.4.1.1 TLK10034 High-Speed Data Path
          2. 6.2.4.1.2 AC-Coupling
          3. 6.2.4.1.3 External Clock Connections
        2. 6.2.4.2 Layout Example
        3. 6.2.4.3 Package Thermal Dissipation Ratings
    3. 6.3 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Mechanical, Packaging, and Orderable Information

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