ZHCSOK0 数据表 | 德州仪器 TI.com.cn

SBOSA91B December 2021 – December 2023 TLV2387 , TLV387 , TLV4387

PRODUCTION DATA

Refer to the PDF data sheet for device specific package drawings

5.8 Typical Characteristics

at T_A = 25°C, V_S = ±2.5 V, V_CM = V_S / 2, R_LOAD = 10 kΩ connected to V_S / 2, and C_L = 50 pF (unless otherwise noted)

V_S = 5.5 V

Figure 5-1 Offset Voltage Drift Distribution

Figure 5-3 Offset Voltage vs Common-Mode Voltage

Figure 5-5 Open-Loop Gain and Phase vs Frequency

Figure 5-7 Closed-Loop Gain and Phase vs Frequency

Figure 5-9 CMRR vs Temperature

Figure 5-11 0.1-Hz to 10-Hz Noise

Figure 5-13 Channel-to-Channel Crosstalk

V_S = 5.5 V, f = 1 kHz, BW = 80 kHz

Figure 5-15 THD+N vs Output Amplitude

Figure 5-17 Quiescent Current vs Temperature

G = –1, 10 mV step

Figure 5-19 Small-Signal Overshoot vs Capacitive Load

Figure 5-21 Phase Margin vs Capacitive Load

G = –1

Figure 5-23 Overload Recovery

Figure 5-25 Large-Signal Step Response (4-V Step)

Figure 5-2 Offset Voltage vs Temperature

Figure 5-4 Offset Voltage vs Supply Voltage

Figure 5-6 Open-Loop Gain vs Temperature

Figure 5-8 Input Bias Current vs Common-Mode Voltage

Figure 5-10 PSRR and CMRR vs Frequency

Figure 5-12 Input Voltage Noise Spectral Density vs Frequency

V_S = 5.5 V, V_OUT = 3 V_RMS, BW = 80 kHz

Figure 5-14 THD+N Ratio vs Frequency

Figure 5-16 Quiescent Current vs Supply Voltage

Figure 5-18 Open-Loop Output Impedance vs Frequency

G = +1, 10 mV step

Figure 5-20 Small-Signal Overshoot vs Capacitive Load

Figure 5-22 No Phase Reversal

G = +1

Figure 5-24 Small-Signal Step Response

0.01% settling = ±100 µV

Figure 5-26 Settling Time