When CLR is high or low, and the comparator is not in a latched condition, the comparator is active ("armed") and responding to the input conditions, ready for the next qualifying condition to latch.

The CLR input only clears the output latch on the high-to-low (falling) edge of the CLR input. The comparator is then active (armed) after the clear until the next latch condition event.

Using the falling-edge to trigger the reset allows the CLR pin to be either a steady high or low, which prevents a hardware or software failure from locking-up the comparator and allows meeting saftey-critical design requirements.

There can be a setup-time contention if the CLR pin is transitioning (falling) at the same time as the comparator output transitions. The output state is indeterminate during the CLR falling edge time. The recommendation is to make the CLR falling-edge as fast as possible to aviod this contention (<100ns fall time).

The CLR pin features a Failsafe, or "5V Compatible" input, accepting logic high levels up to 5V, independent of the comparator supply voltage. The logic high (VOH) threshold is 1.2V.

The CLR input also has a light 200nA active pull-down current to make sure that the CLR pin is low during start-up and the comparator is active. Even with this pull-down, floating the CLR input is not recommended.