SBOS836C March   2020  – March 2021 TLV9041 , TLV9042 , TLV9044

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information for Single Channel
    5. 7.5 Thermal Information for Dual Channel
    6. 7.6 Thermal Information for Quad Channel
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Operating Voltage
      2. 8.3.2  Rail-to-Rail Input
      3. 8.3.3  Rail-to-Rail Output
      4. 8.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5  Capacitive Load and Stability
      6. 8.3.6  Overload Recovery
      7. 8.3.7  EMI Rejection
      8. 8.3.8  Electrical Overstress
      9. 8.3.9  Input and ESD Protection
      10. 8.3.10 Shutdown Function
      11. 8.3.11 Packages With an Exposed Thermal Pad
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV904x Low-Side, Current Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4.     Trademarks
    5. 12.4 Electrostatic Discharge Caution
    6. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)

GUID-20201012-CA0I-HNT1-QFM0-HNNVBLPLV3RN-low.gif
VS = 5.5 V
Figure 7-1 Offset Voltage Distribution Histogram
GUID-20201012-CA0I-4PCV-SLS0-9VRCV1BDHMZ1-low.gif
VS = 5.5 V, VCM = V–
Figure 7-3 Input Offset Voltage vs Temperature
GUID-20201012-CA0I-2HNM-2M3F-DZBJ6XRTGT77-low.gif
 
Figure 7-5 Offset Voltage vs Common-Mode
GUID-20201013-CA0I-VRWX-NRQ3-Z0GKMCKMXK2N-low.gif
VCM = (V–)
Figure 7-7 Offset Voltage vs Supply Voltage
GUID-20201004-CA0I-VCRD-GGTX-7WHNDTCNP344-low.gifFigure 7-9 IB and IOS vs Common-Mode Voltage
GUID-20201005-CA0I-P2G6-CHGH-KPBLT98SJBSL-low.gif
CL = 10 pF
Figure 7-11 Open-Loop Gain and Phase vs Frequency
GUID-20201004-CA0I-7LCD-FZQR-XDVGJB4TSZB0-low.gif
V+ = 2.75 V, V– = –2.75 V RL = 10 kΩ
Figure 7-13 Open-Loop Gain vs Output Voltage
GUID-20201008-CA0I-VHKM-2SMD-QRN7LB7F2QQ4-low.gif
V+ = 2.75 V, V– = –2.75 V
Figure 7-15 Output Voltage vs Output Current (Claw)
GUID-20201005-CA0I-4QPS-LVD5-0Z50T9W9F3VR-low.gif
 
Figure 7-17 PSRR vs Frequency
GUID-20201013-CA0I-XZXS-LXS4-ZQKWFKM674DB-low.gifFigure 7-19 CMRR vs Frequency
GUID-20201005-CA0I-1QN3-JCWF-FKKV0S1SDB7P-low.gifFigure 7-21 0.1 Hz to 10 Hz Voltage Noise in Time Domain
GUID-20201013-CA0I-XJTB-B345-5GP4CGS0RB6P-low.gif
VS = 5.5 V VCM = 2.5 V G = 1
BW = 80 kHz VOUT = 0.5 VRMS
Figure 7-23 THD + N vs Frequency
GUID-20201013-CA0I-GJ7C-9NL7-PJCDXT3KQ22R-low.gif
VS = 5.5 V VCM = 2.5 V f = 1 kHz
G = 1 BW = 80 kHz
Figure 7-25 THD + N vs Amplitude
GUID-20201004-CA0I-2WGJ-TPL9-FWNFPC1CXL23-low.gifFigure 7-27 Quiescent Current vs Supply Voltage
GUID-20201005-CA0I-GT0P-TCHZ-XQVNLVNZZXC8-low.gif
G = 1 VIN = 100 mVpp
Figure 7-29 Small Signal Overshoot vs Capacitive Load
GUID-20201005-CA0I-7RFV-SZG7-D8CVV3ZV3KT7-low.gif
 
Figure 7-31 Phase Margin vs Capacitive Load
GUID-20201009-CA0I-LWZP-BRM0-78BPWTPLLPXD-low.gif
G = –10 VIN = 600 mVPP
Figure 7-33 Overload Recovery
GUID-20201005-CA0I-FZHX-CHWJ-BMBFZQH1GVZ2-low.gif
G = 1 VIN = 4 VPP CL = 10 pF
Figure 7-35 Large-Signal Step Response
GUID-20201009-CA0I-NB8T-Z03R-HV6DXSHNR2SP-low.gif
G = 1 VIN = 4 VPP CL = 10 pF
Figure 7-37 Large-Signal Settling Time (Positive)
GUID-20201005-CA0I-HGHD-3SQP-VLSHTLSNHVX1-low.gifFigure 7-39 Maximum Output Voltage vs Frequency
GUID-20201008-CA0I-LJRJ-XCCN-87ZNSKFNNKWR-low.gifFigure 7-41 Shutdown Mode Quiescent Current vs Supply Voltage
GUID-20201008-CA0I-V4W4-RXKV-PN7FW4TPDBLK-low.gifFigure 7-43 Amplifier Enable Response
GUID-20201008-CA0I-7L1B-3NLW-L8TB88PLDZ3P-low.gifFigure 7-45 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency
GUID-20201004-CA0I-K8QM-60CD-L9RNCRFJK8BJ-low.gif
VS = 5.5 V, TA = –40°C to +125°C
Figure 7-2 Offset Voltage Drift Distribution Histogram
GUID-20201012-CA0I-7BKZ-HBMZ-KCZFW9DRVMMJ-low.gif
VS = 5.5 V, VCM = V+
Figure 7-4 Input Offset Voltage vs Temperature
GUID-20201012-CA0I-RDMQ-WSWL-63G58HS496FM-low.gif
VCM > (V+) – 1.4 V
Figure 7-6 Offset Voltage vs Common-Mode
GUID-20201009-CA0I-XD1Z-NZKC-5Z6FBPBFCDPL-low.gif
 
Figure 7-8 IB and IOS vs Temperature
GUID-20201004-CA0I-MBJD-WCMR-DM6N5SVMMCJW-low.gifFigure 7-10 Open-Loop Gain vs Temperature
GUID-20201008-CA0I-69HW-RSRB-LCLDRQF6RPNP-low.gif
 
Figure 7-12 Open-Loop Output Impedance vs Frequency
GUID-20201005-CA0I-CRJL-DLFC-04SXGLHH6WRR-low.gif
CL = 10 pF
Figure 7-14 Closed-Loop Gain vs Frequency
GUID-20201004-CA0I-FVFR-ZF6Q-0D4VRM0FN6ZV-low.gif
V+ = 0.6 V, V– = –0.6 V
Figure 7-16 Output Voltage vs Output Current (Claw)
GUID-20201004-CA0I-NMNX-C6QK-1DPGH3QRNP35-low.gif
VS = 1.2 V to 5.5 V
Figure 7-18 DC PSRR vs Temperature
GUID-20201004-CA0I-50WC-BM5F-RDQZH598TFHM-low.gifFigure 7-20 DC CMRR vs Temperature
GUID-20201005-CA0I-3NZZ-XFHC-3KGTHSXZVQBN-low.gifFigure 7-22 Input Voltage Noise Spectral Density
GUID-20201013-CA0I-HWMW-VZGD-SQXXKD2KZ56D-low.gif
VS = 5.5 V VCM = 2.5 V G = –1
BW = 80 kHz VOUT = 0.5 VRMS
Figure 7-24 THD + N vs Frequency
GUID-20201013-CA0I-QRTG-GFF9-9PGQDWXLWDMT-low.gif
VS = 5.5 V VCM = 2.5 V f = 1 kHz
G = –1 BW = 80 kHz
Figure 7-26 THD + N vs Amplitude
GUID-20201004-CA0I-XDFN-SRH5-C9GVQKB4MXFD-low.gifFigure 7-28 Quiescent Current vs Temperature
GUID-20201005-CA0I-9N1P-NPCG-MKCPDBQ2DDTV-low.gif
G = –1 VIN = 100 mVpp
Figure 7-30 Small Signal Overshoot vs Capacitive Load
GUID-20201005-CA0I-ZPHQ-VG67-BKF74RDKL5DC-low.gif
G = 1 VIN = 6 VPP
Figure 7-32 No Phase Reversal
GUID-20201005-CA0I-VRNX-KZQX-Q9NZNFJZC4VT-low.gif
G = 1 VIN = 20 mVPP CL = 10 pF
Figure 7-34 Small-Signal Step Response
GUID-20201009-CA0I-ZHKR-MRZJ-4ZXP2KFBZFS7-low.gif
G = 1 VIN = 4 VPP CL = 10 pF
Figure 7-36 Large-Signal Settling Time (Negative)
GUID-20201005-CA0I-TZ9N-TBCN-LXBL6KL7S6PF-low.gif
G = –1 VIN = 4 VPP CL = 10 pF
Figure 7-38 Large-Signal Step Response
GUID-20201009-CA0I-JXMQ-HQMG-0WT4JLDBGHWX-low.gifFigure 7-40 Short-Circuit Current vs Temperature
GUID-20201012-CA0I-BXGG-WCLS-ZKFHMNJXCCGS-low.gifFigure 7-42 Shutdown Mode Quiescent Current vs Temperature
GUID-20201008-CA0I-ZCGH-1BT1-JBHSZPMRTPD8-low.gifFigure 7-44 Amplifier Disable Response
GUID-20201008-CA0I-XCMT-G0KB-TRQXJT4ZSLT7-low.gifFigure 7-46 Channel Separation