SBOS986E October   2019  – January 2022 TLV9151 , TLV9152 , TLV9154

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  EMI Rejection
      2. 7.3.2  Thermal Protection
      3. 7.3.3  Capacitive Load and Stability
      4. 7.3.4  Common-Mode Voltage Range
      5. 7.3.5  Phase Reversal Protection
      6. 7.3.6  Electrical Overstress
      7. 7.3.7  Overload Recovery
      8. 7.3.8  Typical Specifications and Distributions
      9. 7.3.9  Packages With an Exposed Thermal Pad
      10. 7.3.10 Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Side Current Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 TLV9151 DBV Package
5-Pin SOT-23
(Top View)
Figure 5-2 TLV9151 DCK
5-Pin SC70
(Top View)
Table 5-1 Pin Functions: TLV9151
PIN I/O DESCRIPTION
NAME DBV DCK
+IN 3 1 I Noninverting input
–IN 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply
GUID-20200923-CA0I-FHFJ-MWVW-NKKCPKSQXHZR-low.gif Figure 5-3 TLV9151S DBV Package
6-Pin SOT-23
(Top View)
Table 5-2 Pin Functions: TLV9151S
PIN I/O DESCRIPTION
NAME NO.
+IN 3 I Noninverting input
–IN 4 I Inverting input
OUT 1 O Output
SHDN 5 I Shutdown: low = amplifier enabled, high = amplifier disabled. See Shutdown for more information.
V+ 6 — Positive (highest) power supply
V– 2 — Negative (lowest) power supply
Figure 5-4 TLV9152 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23, TSSOP, and VSSOP
(Top View)
Connect thermal pad to V–. See Packages with and Exposed Thermal Pad for more information.
Figure 5-5 TLV9152 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
(Top View)
Table 5-3 Pin Functions: TLV9152
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input, channel A
+IN B 5 I Noninverting input, channel B
–IN A 2 I Inverting input, channel A
–IN B 6 I Inverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
GUID-20200923-CA0I-SVLD-BBNV-0CGFTWNFSL2P-low.gif Figure 5-6 TLV9152S RUG Package
10-Pin X2QFN
(Top View)
Table 5-4 Pin Functions: TLV9152S
PIN I/O DESCRIPTION
NAME NO.
+IN A 10 I Noninverting input, channel A
+IN B 4 I Noninverting input, channel B
–IN A 9 I Inverting input, channel A
–IN B 5 I Inverting input, channel B
OUT A 8 O Output, channel A
OUT B 6 O Output, channel B
SHDN1 2 I Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Shutdown for more information.
SHDN2 3 I Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Shutdown for more information.
V+ 7 — Positive (highest) power supply
V– 1 — Negative (lowest) power supply
Figure 5-7 TLV9154 D, PW, and DYY Packages
14-Pin SOIC, TSSOP, and SOT-23
(Top View)
Figure 5-8 TLV9154 RUC Package
14-Pin X2QFN
(Top View)
Table 5-5 Pin Functions: TLV9154
PIN I/O DESCRIPTION
NAME SOIC, TSSOP, SOT-23 X2QFN
IN1+ 3 2 I Noninverting input, channel 1
IN1– 2 1 I Inverting input, channel 1
IN2+ 5 4 I Noninverting input, channel 2
IN2– 6 5 I Inverting input, channel 2
IN3+ 10 9 I Noninverting input, channel 3
IN3– 9 8 I Inverting input, channel 3
IN4+ 12 11 I Noninverting input, channel 4
IN4– 13 12 I Inverting input, channel 4
NC — — — Do not connect
OUT1 1 14 O Output, channel 1
OUT2 7 6 O Output, channel 2
OUT3 8 7 O Output, channel 3
OUT4 14 13 O Output, channel 4
V+ 4 3 — Positive (highest) power supply
V– 11 10 — Negative (lowest) power supply