Dual 4.5MHz, 16-V rail-to-rail input/output, low-offset voltage, low-noise op amp
Product details
Parameters
Package | Pins | Size
Features
- Low offset voltage: ±125 µV
- Low offset voltage drift: ±0.3 µV/°C
- Low noise: 10.5 nV/√ Hz at 1 kHz
- High common-mode rejection: 120 dB
- Low bias current: ±10 pA
- Rail-to-rail input and output
- Wide bandwidth: 4.5-MHz GBW
- High slew rate: 20 V/µs
- Low quiescent current: 560 µA per amplifier
- Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
- Robust EMIRR performance: EMI/RFI filters on input pins
- Differential and common-mode input voltage range to supply rail
- Industry standard packages:
- Single in SOT-23-5, SC70-5, and SOT553
- Dual in SOIC-8, SOT-23-8, TSSOP-8, VSSOP-8, WSON-8, and X2QFN-10
- Quad in SOIC-14, TSSOP-14, WQFN-14, and WQFN-16
All trademarks are the property of their respective owners.
Description
The TLV915x family (TLV9151, TLV9152, and TLV9154) is a family of 16-V, general purpose operational amplifiers. These devices offer exceptional DC precision and AC performance, including rail-to-rail output, low offset (±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Convenient features such as wide differential input-voltage range, high output current (±75 mA), high slew rate (20 V/µs), and low noise (10.5 nV/√ Hz) make the TLV915x a robust, low-noise operational amplifier for industrial applications.
The TLV915x family of op amps is available in standard packages and is specified from –40°C to 125°C.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp datasheet (Rev. C) | Dec. 21, 2020 |
Technical articles | What is an op amp? | Jan. 21, 2020 | |
Technical articles | How to lay out a PCB for high-performance, low-side current-sensing designs | Feb. 06, 2018 | |
Technical articles | Low-side current sensing for high-performance cost-sensitive applications | Jan. 22, 2018 | |
Technical articles | Voltage and current sensing in HEV/EV applications | Nov. 22, 2017 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Software development
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Features
- Expedites circuit design with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)
- Noise calculations
- Common unit translation
- Solves common amplifier circuit design problems
- Gain selections using standard resistors
- Filter configurations
- Total noise for common amplifier configurations
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 8 | View options |
SOT-23-THIN (DDF) | 8 | View options |
TSSOP (PW) | 8 | View options |
WSON (DSG) | 8 | View options |
X2QFN (RUG) | 10 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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