SLASE75D August   2015  – September 2017 TMDS181

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Electrical Characteristics
    6. 6.6  TMDS Differential Input Electrical Characteristics
    7. 6.7  TMDS Differential Output Electrical Characteristics
    8. 6.8  DDC, I2C, HPD, and ARC Electrical Characteristics
    9. 6.9  Power-Up and Operation Timing Requirements
    10. 6.10 TMDS Switching Characteristics
    11. 6.11 HPD Switching Characteristics
    12. 6.12 DDC and I2C Switching Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Training for HDMI2.0a Data Rate Monitor
      4. 8.4.4 DDC Functional Description
      5. 8.4.5 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 Local I2C Overview
      2. 8.5.2 Local I2C Control Bit Access TAG Convention
      3. 8.5.3 CSR Bit Field Definitions
        1. 8.5.3.1 ID Registers
        2. 8.5.3.2 MISC CONTROL Register
        3. 8.5.3.3 Equalization Control Register
        4. 8.5.3.4 RX PATTERN VERIFIER CONTROL/STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Source Side Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sink Side Application
      3. 9.2.3 Application Chain Showing DDC Connections
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 DDC Pullup Resistors
          2. 9.2.3.1.2 Compliance Testing
            1. 9.2.3.1.2.1 Pin Strapping Configuration for HDMI2.0a and HDMI1.4b
            2. 9.2.3.1.2.2 I2C Control for HDMI2.0a and HDMI1.4b
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
TMDS181 TMDS181I po_LASE75.gif

Pin Functions(2)

PIN TYPE(1) DESCRIPTION
NAME NO.
VCC 13, 43 P 3.3 V power supply
VDD 14, 23, 24, 37, 48 P 1.2 V power supply
GND 7, 19, 41, 30,
Thermal pad		 G Ground
MAIN LINK INPUT PINS
IN_D2p/n 2, 3 I Channel 2 differential input
IN_D1p/n 5, 6 I Channel 1 differential input
IN_D0p/n 8, 9 I Channel 0 differential input
IN_CLKp/n 11, 12 I Clock differential input
MAIN LINK OUTPUT PINS (FAIL SAFE)
OUT_D2n/p 34, 35 O TMDS data 2 differential output
OUT_D1n/p 31, 32 O TMDS data 1 differential output
OUT_D0n/p 28, 29 O TMDS data 0 differential output
OUT_CLKn/p 25, 26 O TMDS data clock differential output
HOT PLUG DETECT PINS
HPD_SRC 4 O Hot plug detect output to source side
HPD_SNK 33 I Hot plug detect input from sink side
AUDIO RETURN CHANNEL AND DDC PINS
SPDIF_IN
ARC_OUT		 45
44		 I/O SPDIF signal input
Audio return channel output
SDA_SRC
SCL_SRC		 47
46		 I/O Source side TMDS port bidirectional DDC data line
Source side TMDS port bidirectional DDC clock line
SDA_SNK
SCL_SNK		 39
38		 I/O Sink side TMDS port bidirectional DDC data line
Sink side TMDS port bidirectional DDC clock line
CONTROL PINS
OE 42 I Operation enable/reset pin
OE = L: Power-down mode
OE = H: Normal operation
Internal weak pull up: Resets device when transitions from H to L
SIG_EN 17 I Signal detector circuit enable
SIG_EN = L: Signal detect circuit disabled:
SIG_EN = H: Signal detect circuit enabled: When no valid clock device enters standby mode.
Internal weak pull down
PRE_SEL 20 I
3 level		 De-emphasis control when I2C_EN/PIN = Low.
PRE_SEL = L: –2 dB
PRE_SEL = No Connect: 0 dB
PRE_SEL = H: Reserved
When I2C_EN/PIN = High de-emphasis is controlled through I2C
EQ_SEL/A0 21 I
3 level		 Input receive equalization pin strap when I2C_EN/PIN = Low
EQ_SEL = L: Fixed EQ at 7.5 dB at 3 GHz
EQ_SEL = No Connect: Adaptive EQ
EQ_SEL = H: Fixed at 14 dB at 3 GHz
When I2C_EN/PIN = High address bit 1
Note: 3 level for pin strap programming but 2 level when I2C address
I2C_EN/PIN 10 I I2C_EN/PIN = High; puts device into I2C Control Mode
I2C_EN/PIN = Low; puts device into pin strap mode
Note: I2C CSR is addressable at all times, but features that can be controlled by pin strapping can only be changed by I2C when this pin is pulled high
SCL_CTL 15 I I2C clock signal
Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be changed by I2C
SDA_CTL 16 I/0 I2C data signal
Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be changed by I2C
VSadj 22 I TMDS-compliant voltage swing control nominal resistor to GND
A1 27 I High address bit 2 for I2C programming
Weak internal pull down
Note: When in Pin Strapping Mode leave pin as No connect
TX_TERM_CTL 36 I
3 level		 Transmit termination control
TX_TERM_CTL = H, no transmit termination
TX_TERM_CTL = L, transmit termination impedance in approximately 75 to 150 Ω
TX_TERM_CTL = No Connect, automatically selects the termination impedance
Data rate (DR) > 3.4 Gbps – 75 to 150 Ω differential near end termination
2 Gbps > DR < 3.4 Gbps – 150 to 300 Ω differential near end termination
DR < 2 Gbps – no termination
Note: If left floating will be in automatic select mode.
SWAP/POL 1 I
3 level		 Input lane SWAP and polarity control pin
SWAP/POL = H: receive lanes polarity swap (retimer mode only)
SWAP/POL = L: receive lanes swap (redriver and retimer mode)
SWAP/POL = No Connect: normal operation
NC 18, 40 NA No connect
(1) G = Ground, I = Input, O = Output, P = Power
(2) (H) Logic high (pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (pin strapped to GND through 65 kΩ resistor); (for mid-level = No connect)