SLASE75D August   2015  – September 2017 TMDS181

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Electrical Characteristics
    6. 6.6  TMDS Differential Input Electrical Characteristics
    7. 6.7  TMDS Differential Output Electrical Characteristics
    8. 6.8  DDC, I2C, HPD, and ARC Electrical Characteristics
    9. 6.9  Power-Up and Operation Timing Requirements
    10. 6.10 TMDS Switching Characteristics
    11. 6.11 HPD Switching Characteristics
    12. 6.12 DDC and I2C Switching Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Training for HDMI2.0a Data Rate Monitor
      4. 8.4.4 DDC Functional Description
      5. 8.4.5 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 Local I2C Overview
      2. 8.5.2 Local I2C Control Bit Access TAG Convention
      3. 8.5.3 CSR Bit Field Definitions
        1. 8.5.3.1 ID Registers
        2. 8.5.3.2 MISC CONTROL Register
        3. 8.5.3.3 Equalization Control Register
        4. 8.5.3.4 RX PATTERN VERIFIER CONTROL/STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Source Side Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sink Side Application
      3. 9.2.3 Application Chain Showing DDC Connections
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 DDC Pullup Resistors
          2. 9.2.3.1.2 Compliance Testing
            1. 9.2.3.1.2.1 Pin Strapping Configuration for HDMI2.0a and HDMI1.4b
            2. 9.2.3.1.2.2 I2C Control for HDMI2.0a and HDMI1.4b
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

To minimize the power consumption of customer application, TMSD181 used the dual power supply. VCC is 3.3 V with 5% range to support the I/O voltage. VDD is 1.2 V to supply the internal digital control circuit. TMDS181 operates in three different working states.

  • Power-down mode:
    • OE = Low puts the device into its lowest power state by shutting down all function blocks.
      • When OE is reasserted, the transitions from L → H create a reset, and if the device is programmed through I2C, it must be reprogrammed.
    • Writing a 1 to register 09h[3].
    • OE = High, HPD_SNK = Low
  • Standby mode: HPD_SNK = High, but no valid clock signal detect on clock lane.
  • Normal operation: Working in redriver or retimer
  • When HPD asserts, the device CDR and output enables based on the signal detector circuit result.
  • HPD_SRC = HPD_SNK in all conditions. The HPD channel is operational when VCC is over 3 V.

NOTE

  1. When the TMDS181 is put into a power-down state, the I2C registers are cleared. This is important as the TMDS_CLOCK_RATIO_STATUS bit will be cleared. If cleared and HDMI2.0 resolutions are to be supported, the TMDS181 expects the source to write a 1 to this bit location. If this does not happen, the PLL will not be set properly and no video may be evident.
  2. Power performance of the TMDS181 is highly dependent upon the HDMI transmitter architecture driving the TMDS181 receiver. The TMDS181 has integrated the termination resistors, which increases the power consumption on the 3.3 V rail by as much as 400 mW. This is the power required by the HDMI transmitter to switch and not needed by the TMDS181 to operate properly.

Table 12. Power-Up and Operation Timing Requirements

INPUTS STATUS
HPD_SNK OE SIG_EN IN_CLK DATA RATE HPD_SRC IN_Dx SDA/SCL_CTL OUT_Dx
OUT_CLK		 DDC ARC MODE
X L H or L X X H RX Termination On Disable High-Z Disabled Disable Power-down mode
L H H or L X X L RX Termination On Active High-Z Disabled Disable Power-down mode
H H H or L X X H RX Termination On Active High-Z Disabled Disable Power-down mode by W 1 to 09h[3]
H H H
(no valid signal)		 No valid TMDS clock X H D0-D2 disabled with RX termination On, IN_CLK active Active High-Z Active Active Standby mode
(squelch waiting)
H H H or L
(no valid signal)		 No valid TMDS clock Retimer mode H D0-D2 disabled with RX termination On, IN_CLK activee Active High-Z Active Active Standby mode
(Squelch waiting)
H H H
(Valid signal)		 Valid TMDS clock Retimer mode H RX active Active TX active Active Active Normal operation
H H L
(no valid signal)		 No valid TMDS clock Redriver mode H RX active Active TX active Active Active Normal operation
H H H
(Valid signal)		 Valid TMDS clock Redriver mode H RX active Active TX active Active Active Normal operation