SPRS880M December   2013  – June 2020 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28378D , TMS320F28379D

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pins With Internal Pullup and Pulldown
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Input X-BAR
      3. 4.4.3 Output X-BAR and ePWM X-BAR
      4. 4.4.4 USB Pin Muxing
      5. 4.4.5 High-Speed SPI Pin Muxing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 Device Current Consumption at 200-MHz SYSCLK
      2. 5.5.1     Current Consumption Graphs
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 ZWT Package
      2. 5.7.2 PTP Package
      3. 5.7.3 PZP Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Sequencing
        1. 5.9.1.1 Signal Pin Requirements
        2. 5.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
        3. 5.9.1.3 VDD Requirements
        4. 5.9.1.4 Supply Ramp Rate
          1. Table 5-3 Supply Ramp Rate
        5. 5.9.1.5 Supply Supervision
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-4 Reset (XRS) Timing Requirements
          2. Table 5-5 Reset (XRS) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-7  Input Clock Frequency
            2. Table 5-8  X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. Table 5-9  X1 Timing Requirements
            4. Table 5-10 AUXCLKIN Timing Requirements
            5. Table 5-11 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-12 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-13 Output Clock Frequency
            2. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-15 Crystal Oscillator Parameters
          2. Table 5-17 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-18 Internal Oscillator Electrical Characteristics
      4. 5.9.4 Flash Parameters
        1. Table 5-20 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-21 JTAG Timing Requirements
          2. Table 5-22 JTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
          1. Table 5-23 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO - Input Timing
          1. Table 5-24 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-25 External Interrupt Timing Requirements
          2. Table 5-26 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Power-Gating Low-Power Modes
        3. 5.9.8.3 Low-Power Mode Wakeup Timing
          1. Table 5-29 IDLE Mode Timing Requirements
          2. Table 5-30 IDLE Mode Switching Characteristics
          3. Table 5-31 STANDBY Mode Timing Requirements
          4. Table 5-32 STANDBY Mode Switching Characteristics
          5. Table 5-33 HALT Mode Timing Requirements
          6. Table 5-34 HALT Mode Switching Characteristics
          7. Table 5-35 HIBERNATE Mode Timing Requirements
          8. Table 5-36 HIBERNATE Mode Switching Characteristics
      9. 5.9.9 External Memory Interface (EMIF)
        1. 5.9.9.1 Asynchronous Memory Support
        2. 5.9.9.2 Synchronous DRAM Support
        3. 5.9.9.3 EMIF Electrical Data and Timing
          1. 5.9.9.3.1 Asynchronous RAM
            1. Table 5-37 EMIF Asynchronous Memory Timing Requirements
            2. Table 5-38 EMIF Asynchronous Memory Switching Characteristics
          2. 5.9.9.3.2 Synchronous RAM
            1. Table 5-39 EMIF Synchronous Memory Timing Requirements
            2. Table 5-40 EMIF Synchronous Memory Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-42 ADC Operating Conditions (16-Bit Differential Mode)
          2. Table 5-43 ADC Characteristics (16-Bit Differential Mode)
          3. Table 5-44 ADC Operating Conditions (12-Bit Single-Ended Mode)
          4. Table 5-45 ADC Characteristics (12-Bit Single-Ended Mode)
          5. Table 5-46 ADCEXTSOC Timing Requirements
          6. 5.10.1.2.1 ADC Input Models
            1. Table 5-47 Differential Input Model Parameters
            2. Table 5-48 Single-Ended Input Model Parameters
          7. 5.10.1.2.2 ADC Timing Diagrams
            1. Table 5-51 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. Table 5-52 ADC Timings in 16-Bit Mode
        3. 5.10.1.3 Temperature Sensor Electrical Data and Timing
          1. Table 5-53 Temperature Sensor Electrical Characteristics
      2. 5.10.2 Comparator Subsystem (CMPSS)
        1. 5.10.2.1 CMPSS Electrical Data and Timing
          1. Table 5-54 Comparator Electrical Characteristics
          2. Table 5-55 CMPSS DAC Static Electrical Characteristics
      3. 5.10.3 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.3.1 Buffered DAC Electrical Data and Timing
          1. Table 5-56 Buffered DAC Electrical Characteristics
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-57 eCAP Timing Requirement
          2. Table 5-58 eCAP Switching Characteristics
      2. 5.11.2 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.2.1 Control Peripherals Synchronization
        2. 5.11.2.2 ePWM Electrical Data and Timing
          1. Table 5-59 ePWM Timing Requirements
          2. Table 5-60 ePWM Switching Characteristics
          3. 5.11.2.2.1 Trip-Zone Input Timing
            1. Table 5-61 Trip-Zone Input Timing Requirements
        3. 5.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-62 External ADC Start-of-Conversion Switching Characteristics
      3. 5.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.3.1 eQEP Electrical Data and Timing
          1. Table 5-63 eQEP Timing Requirements
          2. Table 5-64 eQEP Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-65 High-Resolution PWM Timing Requirements
          2. Table 5-66 High-Resolution PWM Characteristics
      5. 5.11.5 Sigma-Delta Filter Module (SDFM)
        1. 5.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. Table 5-67 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
          1. Table 5-68 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-69 I2C Timing Requirements
          2. Table 5-70 I2C Switching Characteristics
      3. 5.12.3 Multichannel Buffered Serial Port (McBSP)
        1. 5.12.3.1 McBSP Electrical Data and Timing
          1. 5.12.3.1.1 McBSP Transmit and Receive Timing
            1. Table 5-71 McBSP Timing Requirements
            2. Table 5-72 McBSP Switching Characteristics
          2. 5.12.3.1.2 McBSP as SPI Master or Slave Timing
            1. Table 5-73 McBSP as SPI Master Timing Requirements
            2. Table 5-74 McBSP as SPI Master Switching Characteristics
            3. Table 5-75 McBSP as SPI Slave Timing Requirements
            4. Table 5-76 McBSP as SPI Slave Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 SPI Master Mode Timings
            1. Table 5-77 SPI Master Mode Timing Requirements
            2. Table 5-78 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. Table 5-79 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 5.12.5.1.2 SPI Slave Mode Timings
            1. Table 5-80 SPI Slave Mode Timing Requirements
            2. Table 5-81 SPI Slave Mode Switching Characteristics
      6. 5.12.6 Universal Serial Bus (USB) Controller
        1. 5.12.6.1 USB Electrical Data and Timing
          1. Table 5-82 USB Input Ports DP and DM Timing Requirements
          2. Table 5-83 USB Output Ports DP and DM Switching Characteristics
      7. 5.12.7 Universal Parallel Port (uPP) Interface
        1. 5.12.7.1 uPP Electrical Data and Timing
          1. Table 5-84 uPP Timing Requirements
          2. Table 5-85 uPP Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Flash Memory Map
      3. 6.3.3 EMIF Chip Select Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CPU Message RAM (CPU MSGRAM)
        5. 6.3.5.5 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Floating-Point Unit
      2. 6.6.2 Trigonometric Math Unit
      3. 6.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)
    7. 6.7  Control Law Accelerator
    8. 6.8  Direct Memory Access
    9. 6.9  Interprocessor Communication Module
    10. 6.10 Boot ROM and Peripheral Booting
      1. 6.10.1 EMU Boot or Emulation Boot
      2. 6.10.2 WAIT Boot Mode
      3. 6.10.3 Get Mode
      4. 6.10.4 Peripheral Pins Used by Bootloaders
    11. 6.11 Dual Code Security Module
    12. 6.12 Timers
    13. 6.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    14. 6.14 Watchdog
    15. 6.15 Configurable Logic Block (CLB)
    16. 6.16 Functional Safety
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Peripheral Registers Memory Map

The peripheral registers memory map can be found in Table 6-5. The peripheral registers can be assigned to either the CPU1 or CPU2 subsystems except where noted in Table 6-5. Registers in the peripheral frames share a secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See the TMS320F2837xD Dual-Core Microcontrollers Technical Reference Manual for details on the CPU subsystem and secondary master selection.

Table 6-5 Peripheral Registers Memory Map

REGISTERS STRUCTURE NAME START
ADDRESS
END
ADDRESS
PROTECTED(1) CLA
ACCESS
DMA
ACCESS
AdcaResultRegs ADC_RESULT_REGS 0x0000 0B00 0x0000 0B1F Yes Yes
AdcbResultRegs ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes
AdccResultRegs ADC_RESULT_REGS 0x0000 0B40 0x0000 0B5F Yes Yes
AdcdResultRegs ADC_RESULT_REGS 0x0000 0B60 0x0000 0B7F Yes Yes
CpuTimer0Regs(2) CPUTIMER_REGS 0x0000 0C00 0x0000 0C07
CpuTimer1Regs(2) CPUTIMER_REGS 0x0000 0C08 0x0000 0C0F
CpuTimer2Regs(2) CPUTIMER_REGS 0x0000 0C10 0x0000 0C17
PieCtrlRegs(2)(5) PIE_CTRL_REGS 0x0000 0CE0 0x0000 0CFF
Cla1SoftIntRegs(5) CLA_SOFTINT_REGS 0x0000 0CE0 0x0000 0CFF Yes – CLA only, no CPU access
DmaRegs(2) DMA_REGS 0x0000 1000 0x0000 11FF
Cla1Regs(2) CLA_REGS 0x0000 1400 0x0000 147F
Peripheral Frame 1
EPwm1Regs EPWM_REGS 0x0000 4000 0x0000 40FF Yes Yes Yes
EPwm2Regs EPWM_REGS 0x0000 4100 0x0000 41FF Yes Yes Yes
EPwm3Regs EPWM_REGS 0x0000 4200 0x0000 42FF Yes Yes Yes
EPwm4Regs EPWM_REGS 0x0000 4300 0x0000 43FF Yes Yes Yes
EPwm5Regs EPWM_REGS 0x0000 4400 0x0000 44FF Yes Yes Yes
EPwm6Regs EPWM_REGS 0x0000 4500 0x0000 45FF Yes Yes Yes
EPwm7Regs EPWM_REGS 0x0000 4600 0x0000 46FF Yes Yes Yes
EPwm8Regs EPWM_REGS 0x0000 4700 0x0000 47FF Yes Yes Yes
EPwm9Regs EPWM_REGS 0x0000 4800 0x0000 48FF Yes Yes Yes
EPwm10Regs EPWM_REGS 0x0000 4900 0x0000 49FF Yes Yes Yes
EPwm11Regs EPWM_REGS 0x0000 4A00 0x0000 4AFF Yes Yes Yes
EPwm12Regs EPWM_REGS 0x0000 4B00 0x0000 4BFF Yes Yes Yes
ECap1Regs ECAP_REGS 0x0000 5000 0x0000 501F Yes Yes Yes
ECap2Regs ECAP_REGS 0x0000 5020 0x0000 503F Yes Yes Yes
ECap3Regs ECAP_REGS 0x0000 5040 0x0000 505F Yes Yes Yes
ECap4Regs ECAP_REGS 0x0000 5060 0x0000 507F Yes Yes Yes
ECap5Regs ECAP_REGS 0x0000 5080 0x0000 509F Yes Yes Yes
ECap6Regs ECAP_REGS 0x0000 50A0 0x0000 50BF Yes Yes Yes
EQep1Regs EQEP_REGS 0x0000 5100 0x0000 513F Yes Yes Yes
EQep2Regs EQEP_REGS 0x0000 5140 0x0000 517F Yes Yes Yes
EQep3Regs EQEP_REGS 0x0000 5180 0x0000 51BF Yes Yes Yes
DacaRegs DAC_REGS 0x0000 5C00 0x0000 5C0F Yes Yes Yes
DacbRegs DAC_REGS 0x0000 5C10 0x0000 5C1F Yes Yes Yes
DaccRegs DAC_REGS 0x0000 5C20 0x0000 5C2F Yes Yes Yes
Cmpss1Regs CMPSS_REGS 0x0000 5C80 0x0000 5C9F Yes Yes Yes
Cmpss2Regs CMPSS_REGS 0x0000 5CA0 0x0000 5CBF Yes Yes Yes
Cmpss3Regs CMPSS_REGS 0x0000 5CC0 0x0000 5CDF Yes Yes Yes
Cmpss4Regs CMPSS_REGS 0x0000 5CE0 0x0000 5CFF Yes Yes Yes
Cmpss5Regs CMPSS_REGS 0x0000 5D00 0x0000 5D1F Yes Yes Yes
Cmpss6Regs CMPSS_REGS 0x0000 5D20 0x0000 5D3F Yes Yes Yes
Cmpss7Regs CMPSS_REGS 0x0000 5D40 0x0000 5D5F Yes Yes Yes
Cmpss8Regs CMPSS_REGS 0x0000 5D60 0x0000 5D7F Yes Yes Yes
Sdfm1Regs SDFM_REGS 0x0000 5E00 0x0000 5E7F Yes Yes Yes
Sdfm2Regs SDFM_REGS 0x0000 5E80 0x0000 5EFF Yes Yes Yes
Peripheral Frame 2
McbspaRegs MCBSP_REGS 0x0000 6000 0x0000 603F Yes Yes Yes
McbspbRegs MCBSP_REGS 0x0000 6040 0x0000 607F Yes Yes Yes
SpiaRegs SPI_REGS 0x0000 6100 0x0000 610F Yes Yes Yes
SpibRegs SPI_REGS 0x0000 6110 0x0000 611F Yes Yes Yes
SpicRegs SPI_REGS 0x0000 6120 0x0000 612F Yes Yes Yes
UppRegs(3) UPP_REGS 0x0000 6200 0x0000 62FF Yes Yes Yes
 
WdRegs(2) WD_REGS 0x0000 7000 0x0000 703F Yes
NmiIntruptRegs(2) NMI_INTRUPT_REGS 0x0000 7060 0x0000 706F Yes
XintRegs(2) XINT_REGS 0x0000 7070 0x0000 707F Yes
SciaRegs SCI_REGS 0x0000 7200 0x0000 720F Yes
ScibRegs SCI_REGS 0x0000 7210 0x0000 721F Yes
ScicRegs SCI_REGS 0x0000 7220 0x0000 722F Yes
ScidRegs SCI_REGS 0x0000 7230 0x0000 723F Yes
I2caRegs I2C_REGS 0x0000 7300 0x0000 733F Yes
I2cbRegs I2C_REGS 0x0000 7340 0x0000 737F Yes
AdcaRegs ADC_REGS 0x0000 7400 0x0000 747F Yes Yes
AdcbRegs ADC_REGS 0x0000 7480 0x0000 74FF Yes Yes
AdccRegs ADC_REGS 0x0000 7500 0x0000 757F Yes Yes
AdcdRegs ADC_REGS 0x0000 7580 0x0000 75FF Yes Yes
InputXbarRegs(3) INPUT_XBAR_REGS 0x0000 7900 0x0000 791F Yes
XbarRegs(3) XBAR_REGS 0x0000 7920 0x0000 793F Yes
TrigRegs(3) TRIG_REGS 0x0000 7940 0x0000 794F Yes
DmaClaSrcSelRegs(2) DMA_CLA_SRC_SEL_REGS 0x0000 7980 0x0000 798F Yes
EPwmXbarRegs(3) EPWM_XBAR_REGS 0x0000 7A00 0x0000 7A3F Yes
OutputXbarRegs(3) OUTPUT_XBAR_REGS 0x0000 7A80 0x0000 7ABF Yes
GpioCtrlRegs(3) GPIO_CTRL_REGS 0x0000 7C00 0x0000 7D7F Yes
GpioDataRegs(2) GPIO_DATA_REGS 0x0000 7F00 0x0000 7F2F Yes Yes
UsbaRegs(3) USB_REGS 0x0004 0000 0x0004 0FFF Yes
Emif1Regs EMIF_REGS 0x0004 7000 0x0004 77FF Yes
Emif2Regs(3) EMIF_REGS 0x0004 7800 0x0004 7FFF Yes
CanaRegs CAN_REGS 0x0004 8000 0x0004 87FF Yes
CanbRegs CAN_REGS 0x0004 A000 0x0004 A7FF Yes
IpcRegs(2) IPC_REGS_CPU1
IPC_REGS_CPU2
0x0005 0000 0x0005 0023 Yes
FlashPumpSemaphoreRegs(2) FLASH_PUMP_SEMAPHORE_REGS 0x0005 0024 0x0005 0025 Yes
DevCfgRegs(3) DEV_CFG_REGS 0x0005 D000 0x0005 D17F Yes
AnalogSubsysRegs(3) ANALOG_SUBSYS_REGS 0x0005 D180 0x0005 D1FF Yes
ClkCfgRegs(4) CLK_CFG_REGS 0x0005 D200 0x0005 D2FF Yes
CpuSysRegs(2) CPU_SYS_REGS 0x0005 D300 0x0005 D3FF Yes
RomPrefetchRegs(3) ROM_PREFETCH_REGS 0x0005 E608 0x0005 E60B Yes
DcsmZ1Regs(2) DCSM_Z1_REGS 0x0005 F000 0x0005 F02F Yes
DcsmZ2Regs(2) DCSM_Z2_REGS 0x0005 F040 0x0005 F05F Yes
DcsmCommonRegs(2) DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F Yes
MemCfgRegs(2) MEM_CFG_REGS 0x0005 F400 0x0005 F47F Yes
Emif1ConfigRegs(2) EMIF1_CONFIG_REGS 0x0005 F480 0x0005 F49F Yes
Emif2ConfigRegs(3) EMIF2_CONFIG_REGS 0x0005 F4A0 0x0005 F4BF Yes
AccessProtectionRegs(2) ACCESS_PROTECTION_REGS 0x0005 F4C0 0x0005 F4FF Yes
MemoryErrorRegs(2) MEMORY_ERROR_REGS 0x0005 F500 0x0005 F53F Yes
RomWaitStateRegs(3) ROM_WAIT_STATE_REGS 0x0005 F540 0x0005 F541 Yes
Flash0CtrlRegs(2) FLASH_CTRL_REGS 0x0005 F800 0x0005 FAFF Yes
Flash0EccRegs(2) FLASH_ECC_REGS 0x0005 FB00 0x0005 FB3F Yes
  1. The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that follows a write operation within a protected address range is executed as written by delaying the read operation until the write is initiated.
  2. A unique copy of these registers exist on each CPU subsystem.
  3. These registers are available only on the CPU1 subsystem.
  4. These registers are mapped to either CPU1 or CPU2 based on a semaphore.
  5. The address overlap of PieCtrlRegs and Cla1SoftIntRegs is correct. Each CPU, C28x and CLA, only has access to one of the register sets.