SPRSP85 April   2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PDT Package
    8. 6.8  Thermal Resistance Characteristics for PZ Package
    9. 6.9  Thermal Resistance Characteristics for PNA Package
    10. 6.10 Thermal Resistance Characteristics for PM Package
    11. 6.11 Thermal Resistance Characteristics for RSH Package
    12. 6.12 Thermal Design Considerations
    13. 6.13 System
      1. 6.13.1  Power Management Module (PMM)
        1. 6.13.1.1 Introduction
        2. 6.13.1.2 Overview
          1. 6.13.1.2.1 Power Rail Monitors
            1. 6.13.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.13.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.13.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.13.1.2.2 External Supervisor Usage
          3. 6.13.1.2.3 Delay Blocks
          4. 6.13.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.13.1.2.5 VREGENZ
        3. 6.13.1.3 External Components
          1. 6.13.1.3.1 Decoupling Capacitors
            1. 6.13.1.3.1.1 VDDIO Decoupling
            2. 6.13.1.3.1.2 VDD Decoupling
        4. 6.13.1.4 Power Sequencing
          1. 6.13.1.4.1 Supply Pins Ganging
          2. 6.13.1.4.2 Signal Pins Power Sequence
          3. 6.13.1.4.3 Supply Pins Power Sequence
            1. 6.13.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.13.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.13.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.13.1.4.3.4 Supply Slew Rate
        5. 6.13.1.5 Power Management Module Electrical Data and Timing
          1. 6.13.1.5.1 Power Management Module Operating Conditions
          2. 6.13.1.5.2 Power Management Module Characteristics
      2. 6.13.2  Reset Timing
        1. 6.13.2.1 Reset Sources
        2. 6.13.2.2 Reset Electrical Data and Timing
          1. 6.13.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.13.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.13.2.2.3 Reset Timing Diagrams
      3. 6.13.3  Clock Specifications
        1. 6.13.3.1 Clock Sources
        2. 6.13.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.13.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.13.3.2.1.1 Input Clock Frequency
            2. 6.13.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.13.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.13.3.2.1.4 X1 Timing Requirements
            5. 6.13.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.13.3.2.1.6 APLL Characteristics
            7. 6.13.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.13.3.2.1.8 Internal Clock Frequencies
        3. 6.13.3.3 Input Clocks and PLLs
        4. 6.13.3.4 XTAL Oscillator
          1. 6.13.3.4.1 Introduction
          2. 6.13.3.4.2 Overview
            1. 6.13.3.4.2.1 Electrical Oscillator
              1. 6.13.3.4.2.1.1 Modes of Operation
                1. 6.13.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.13.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.13.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.13.3.4.2.2 Quartz Crystal
            3. 6.13.3.4.2.3 GPIO Modes of Operation
          3. 6.13.3.4.3 Functional Operation
            1. 6.13.3.4.3.1 ESR – Effective Series Resistance
            2. 6.13.3.4.3.2 Rneg – Negative Resistance
            3. 6.13.3.4.3.3 Start-up Time
              1. 6.13.3.4.3.3.1 X1/X2 Precondition
            4. 6.13.3.4.3.4 DL – Drive Level
          4. 6.13.3.4.4 How to Choose a Crystal
          5. 6.13.3.4.5 Testing
          6. 6.13.3.4.6 Common Problems and Debug Tips
          7. 6.13.3.4.7 Crystal Oscillator Specifications
            1. 6.13.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.13.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.13.3.4.7.3 Crystal Oscillator Parameters
            4. 6.13.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.13.3.5 Internal Oscillators
          1. 6.13.3.5.1 INTOSC Characteristics
      4. 6.13.4  Flash Parameters
        1. 6.13.4.1 Flash Parameters 
      5. 6.13.5  RAM Specifications
      6. 6.13.6  ROM Specifications
      7. 6.13.7  Emulation/JTAG
        1. 6.13.7.1 JTAG Electrical Data and Timing
          1. 6.13.7.1.1 JTAG Timing Requirements
          2. 6.13.7.1.2 JTAG Switching Characteristics
          3. 6.13.7.1.3 JTAG Timing Diagram
        2. 6.13.7.2 cJTAG Electrical Data and Timing
          1. 6.13.7.2.1 cJTAG Timing Requirements
          2. 6.13.7.2.2 cJTAG Switching Characteristics
          3. 6.13.7.2.3 cJTAG Timing Diagram
      8. 6.13.8  GPIO Electrical Data and Timing
        1. 6.13.8.1 GPIO – Output Timing
          1. 6.13.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.13.8.1.2 General-Purpose Output Timing Diagram
        2. 6.13.8.2 GPIO – Input Timing
          1. 6.13.8.2.1 General-Purpose Input Timing Requirements
          2. 6.13.8.2.2 Sampling Mode
        3. 6.13.8.3 Sampling Window Width for Input Signals
      9. 6.13.9  Interrupts
        1. 6.13.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.13.9.1.1 External Interrupt Timing Requirements
          2. 6.13.9.1.2 External Interrupt Switching Characteristics
          3. 6.13.9.1.3 External Interrupt Timing
      10. 6.13.10 Low-Power Modes
        1. 6.13.10.1 Clock-Gating Low-Power Modes
        2. 6.13.10.2 Low-Power Mode Wake-up Timing
          1. 6.13.10.2.1 IDLE Mode Timing Requirements
          2. 6.13.10.2.2 IDLE Mode Switching Characteristics
          3. 6.13.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.13.10.2.4 STANDBY Mode Timing Requirements
          5. 6.13.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.13.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.13.10.2.7 HALT Mode Timing Requirements
          8. 6.13.10.2.8 HALT Mode Switching Characteristics
          9. 6.13.10.2.9 HALT Entry and Exit Timing Diagram
    14. 6.14 Analog Peripherals
      1. 6.14.1 Block Diagram
      2. 6.14.2 Analog Pins and Internal Connections
      3. 6.14.3 Analog Signal Descriptions
      4. 6.14.4 Analog-to-Digital Converter (ADC)
        1. 6.14.4.1 ADC Configurability
          1. 6.14.4.1.1 Signal Mode
        2. 6.14.4.2 ADC Electrical Data and Timing
          1. 6.14.4.2.1 ADC Operating Conditions
          2. 6.14.4.2.2 ADC Characteristics
          3. 6.14.4.2.3 ADC INL and DNL
          4. 6.14.4.2.4 ADC Input Model
          5. 6.14.4.2.5 ADC Timing Diagrams
      5. 6.14.5 Temperature Sensor
        1. 6.14.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.14.5.1.1 Temperature Sensor Characteristics
      6. 6.14.6 Comparator Subsystem (CMPSS)
        1. 6.14.6.1 CMPx_DACL
        2. 6.14.6.2 CMPSS Connectivity Diagram
        3. 6.14.6.3 Block Diagram
        4. 6.14.6.4 CMPSS Electrical Data and Timing
          1. 6.14.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.14.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.14.6.4.3 CMPSS Illustrative Graphs
          5. 6.14.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.14.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.14.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.14.7.1 Buffered DAC Electrical Data and Timing
          1. 6.14.7.1.1 Buffered DAC Operating Conditions
          2. 6.14.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.14.8 Programmable Gain Amplifier (PGA)
        1. 6.14.8.1 PGA Electrical Data and Timing
          1. 6.14.8.1.1 PGA Operating Conditions
          2. 6.14.8.1.2 PGA Characteristics
    15. 6.15 Control Peripherals
      1. 6.15.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.15.1.1 Control Peripherals Synchronization
        2. 6.15.1.2 ePWM Electrical Data and Timing
          1. 6.15.1.2.1 ePWM Timing Requirements
          2. 6.15.1.2.2 ePWM Switching Characteristics
          3. 6.15.1.2.3 Trip-Zone Input Timing
            1. 6.15.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.15.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.15.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.15.2.1 HRPWM Electrical Data and Timing
          1. 6.15.2.1.1 High-Resolution PWM Characteristics
      3. 6.15.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.15.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.15.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.15.4 Enhanced Capture (eCAP)
        1. 6.15.4.1 eCAP Block Diagram
        2. 6.15.4.2 eCAP Synchronization
        3. 6.15.4.3 eCAP Electrical Data and Timing
          1. 6.15.4.3.1 eCAP Timing Requirements
          2. 6.15.4.3.2 eCAP Switching Characteristics
      5. 6.15.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.15.5.1 eQEP Electrical Data and Timing
          1. 6.15.5.1.1 eQEP Timing Requirements
          2. 6.15.5.1.2 eQEP Switching Characteristics
    16. 6.16 Communications Peripherals
      1. 6.16.1 Modular Controller Area Network (MCAN)
      2. 6.16.2 Inter-Integrated Circuit (I2C)
        1. 6.16.2.1 I2C Electrical Data and Timing
          1. 6.16.2.1.1 I2C Timing Requirements
          2. 6.16.2.1.2 I2C Switching Characteristics
          3. 6.16.2.1.3 I2C Timing Diagram
      3. 6.16.3 Power Management Bus (PMBus) Interface
        1. 6.16.3.1 PMBus Electrical Data and Timing
          1. 6.16.3.1.1 PMBus Electrical Characteristics
          2. 6.16.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.16.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.16.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.16.4 Serial Communications Interface (SCI)
      5. 6.16.5 Serial Peripheral Interface (SPI)
        1. 6.16.5.1 SPI Controller Mode Timings
          1. 6.16.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.16.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.16.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.16.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.16.5.2 SPI Peripheral Mode Timings
          1. 6.16.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.16.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.16.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.16.6 Local Interconnect Network (LIN)
      7. 6.16.7 Fast Serial Interface (FSI)
        1. 6.16.7.1 FSI Transmitter
          1. 6.16.7.1.1 FSITX Electrical Data and Timing
            1. 6.16.7.1.1.1 FSITX Switching Characteristics
            2. 6.16.7.1.1.2 FSITX Timings
        2. 6.16.7.2 FSI Receiver
          1. 6.16.7.2.1 FSIRX Electrical Data and Timing
            1. 6.16.7.2.1.1 FSIRX Timing Requirements
            2. 6.16.7.2.1.2 FSIRX Switching Characteristics
            3. 6.16.7.2.1.3 FSIRX Timings
        3. 6.16.7.3 FSI SPI Compatibility Mode
          1. 6.16.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.16.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.16.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.16.8 Universal Serial Bus (USB)
        1. 6.16.8.1 USB Electrical Data and Timing
          1. 6.16.8.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.16.8.1.2 USB Output Ports DP and DM Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 TI Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     TAPE AND REEL INFORMATION
    2.     TRAY

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
  • PTF|128
  • PDT|128
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10.1.1 Configuring Boot Mode Pins

This section explains how the boot mode select pins can be customized by the user, by programming the BOOTPIN-CONFIG location (refer to Table 7-9) in the user-configurable dual-zone security module (DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG. When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTP-BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP. The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.

Note:

When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will take priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTP-BOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTP-BOOTPIN-CONFIG.

Table 7-9 BOOTPIN-CONFIG Bit Fields
BITNAMEDESCRIPTION
31:24KeyWrite 0x5A to these 8-bits to indicate the bits in this register are valid
23:16Boot Mode Select Pin 2 (BMSP2)Refer to BMSP0 description except for BMSP2
15:8Boot Mode Select Pin 1 (BMSP1)Refer to BMSP0 description except for BMSP1
7:0Boot Mode Select Pin 0 (BMSP0)

Set to the GPIO pin to be used during boot (up to 255):
- 0x0 = GPIO0
- 0x01 = GPIO1
- and so on

Writing 0xFF disables BMSP0 and this pin is no longer used to select the boot mode.

The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM automatically selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the BMSP).

  • GPIO 20 and GPIO 21
  • GPIO 36 and GPIO 38
  • GPIO 62 to GPIO 223

Table 7-10 Standalone Boot Mode Select Pin Decoding
BOOTPIN_CONFIG
KEY		BMSP0BMSP1BMSP2REALIZED BOOT MODE
!= 0x5ADon’t CareDon’t CareDon’t CareBoot as defined by the factory default BMSPs
= 0x5A0xFF0xFF0xFFBoot as defined in the boot table for boot mode 0
(All BMSPs disabled)
Valid GPIO0xFF0xFFBoot as defined by the value of BMSP0
(BMSP1 and BMSP2 disabled)
0xFFValid GPIO0xFFBoot as defined by the value of BMSP1
(BMSP0 and BMSP2 disabled)
0xFF0xFFValid GPIOBoot as defined by the value of BMSP2
(BMSP0 and BMSP1 disabled)
Valid GPIOValid GPIO0xFFBoot as defined by the values of BMSP0 and BMSP1
(BMSP2 disabled)
Valid GPIO0xFFValid GPIOBoot as defined by the values of BMSP0 and BMSP2
(BMSP1 disabled)
0xFFValid GPIOValid GPIOBoot as defined by the values of BMSP1 and BMSP2
(BMSP0 disabled)
Valid GPIOValid GPIOValid GPIOBoot as defined by the values of BMSP0, BMSP1, and BMSP2
Invalid GPIOValid GPIOValid GPIOBMSP0 is reset to the factory default BMSP0 GPIO
Boot as defined by the values of BMSP0, BMSP1, and BMSP2
Valid GPIOInvalid GPIOValid GPIOBMSP1 is reset to the factory default BMSP1 GPIO
Boot as defined by the values of BMSP0, BMSP1, and BMSP2
Valid GPIOValid GPIOInvalid GPIOBMSP2 is reset to the factory default state, which is disabled
Boot as defined by the values of BMSP0 and BMSP1

 

Note:

When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significant-bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled), then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0, then the selectable boot table indexes are 0 and 1.