SCDS412A June   2019  – August 2019 TMUX1133 , TMUX1134

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      TMUX113x Block Diagrams
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions TMUX1133
    2.     Pin Functions TMUX1134
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics (VDD = 5 V ±10 %)
    6. 7.6  Electrical Characteristics (VDD = 3.3 V ±10 %)
    7. 7.7  Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %)
    8. 7.8  Electrical Characteristics (VDD = 1.8 V ±10 %)
    9. 7.9  Electrical Characteristics (VDD = 1.2 V ±10 %)
    10. 7.10 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Transition Time
    5. 8.5  Break-Before-Make
    6. 8.6  tON(EN) and tOFF(EN)
    7. 8.7  Charge Injection
    8. 8.8  Off Isolation
    9. 8.9  Crosstalk
    10. 8.10 Bandwidth
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Rail to Rail Operation
      3. 9.3.3 1.8 V Logic Compatible Inputs
      4. 9.3.4 Fail-Safe Logic
      5. 9.3.5 Ultra-low Leakage Current
      6. 9.3.6 Ultra-low Charge Injection
    4. 9.4 Device Functional Modes
    5. 9.5 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Design Requirements
    4. 10.4 Detailed Design Procedure
    5. 10.5 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layout Information
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Information

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners.Figure 32 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.

TMUX1133 TMUX1134 layout_scds357.gifFigure 32. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies.

Figure 33 and Figure 34 illustrate examples of a PCB layout with the TMUX1133 and TMUX1134 respectively. Some key considerations are:

  • Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
  • Keep the input lines as short as possible.
  • Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.