SCDS436A September   2023  – December 2024 TMUX9616 , TMUX9616N

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics: TMUX9616
    6. 5.6 Switching Characteristics: TMUX9616
    7. 5.7 Digital Timings: TMUX9616
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Off-Leakage Current
    2. 6.2 Device Turn On/Off Time
    3. 6.3 Off Isolation
    4. 6.4 Inter-Channel Crosstalk
    5. 6.5 Output Voltage Spike
    6. 6.6 Switch DC Offset Voltage
    7. 6.7 Isolation Diode Current
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wide Input Signal Range (up to ±110 V, 220 VPP)
      2. 7.3.2 Bidirectional Operation
      3. 7.3.3 Device Digital Logic Control
      4. 7.3.4 Latch-Up Immunity by Device Construction
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Device Power Up
    5. 7.5 Device Logic Table
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Device Logic Table

Table 7-1 Device Logic Table(1)(2)(3)(4)(5)(6)(7)
Inputs Outputs
D0 D1 ... D15 LE CLR SW0 SW1 ... SW15
0 — ... — L L OFF — ... —
1 — — L L ON — —
— 0 — L L — OFF —
— 1 — L L — ON —
— — — L L — — —
— — — L L — — —
— — 0 L L — — OFF
— — 1 L L — — ON
X X X X H L HOLD PREVIOUS STATE
X X X X X H OFF OFF OFF OFF
(1) All 16 switches operate independently.
(2) Serial data is clocked in on the rising edge of CLK. Data is shifted in on the DIN pin with the most-significant bit (MSB) first.
(3) The switches go to a state of retaining their present state on the rising edge of the LE pin. Once the LE pin is high, updates to the shift register no longer change the condition of the 16 switches until the LE pin is made low again. When the LE is low, the shift register data flows through the latch.
(4) Shift register clocking has no effect on the switch states if the LE pin is high.
(5) DOUT is the data output pin of the 16 bit shift register for daisy chaining multiple muxes together. It is the data of the DIN clock shifted by the 16 clock cycles.
(6) The CLR input overrides all other inputs.
(7) While LE = H or CLR = H, if the CLK pin still receiving a valid clock signal, DIN will still function and input data into the shift register, and DOUT will still output the contents on the shift register. However, while LE = H or CLR = H, the state of the analog switches is no longer dependent on the contents of the shift register, but rather takes the state per this logic table.