SCDS436A September   2023  – December 2024 TMUX9616 , TMUX9616N

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics: TMUX9616
    6. 5.6 Switching Characteristics: TMUX9616
    7. 5.7 Digital Timings: TMUX9616
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Off-Leakage Current
    2. 6.2 Device Turn On/Off Time
    3. 6.3 Off Isolation
    4. 6.4 Inter-Channel Crosstalk
    5. 6.5 Output Voltage Spike
    6. 6.6 Switch DC Offset Voltage
    7. 6.7 Isolation Diode Current
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wide Input Signal Range (up to ±110 V, 220 VPP)
      2. 7.3.2 Bidirectional Operation
      3. 7.3.3 Device Digital Logic Control
      4. 7.3.4 Latch-Up Immunity by Device Construction
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Device Power Up
    5. 7.5 Device Logic Table
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Digital Timings: TMUX9616

VDD = 4.5V - 5.5V, VLL = 1.7V - 5.5V, GND = 0 V (unless otherwise noted) 
Typical at VDD = 5 V, VLL = 3.3V, TA = 25℃  (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
fCLK_SPI SPI Clock Frequency (including daisy chain mode) VLL = 5V –40°C to +85°C 72 MHz
fCLK_SPI SPI Clock Frequency (including daisy chain mode) VLL = 3.3V –40°C to +85°C 54 MHz
fCLK_SPI SPI Clock Frequency (including daisy chain mode) VLL = 1.8V –40°C to +85°C 24 MHz
tR, tF_SPI SPI Clock Rise and Fall Times –40°C to +85°C 50 ns
tCLK_SPI CLK SPI Period VLL = 5V –40°C to +85°C 11.76 ns
tCLK_SPI CLK SPI Period VLL = 3.3V –40°C to +85°C 16.67 ns
tCLK_SPI CLK SPI Period VLL = 1.8V –40°C to +85°C 41.67 ns
tCLK_H_SPI CLK High Time SPI VLL = 5V –40°C to +85°C 5.29 ns
tCLK_H_SPI CLK High Time SPI VLL = 3.3V –40°C to +85°C 7.5 ns
tCLK_H_SPI CLK High Time SPI VLL = 1.8V –40°C to +85°C 18.75 ns
tCLK_L_SPI CLK Low Time SPI VLL = 5V –40°C to +85°C 5.29 ns
tCLK_L_SPI CLK Low Time SPI VLL = 3.3V –40°C to +85°C 7.5 ns
tCLK_L_SPI CLK Low Time SPI VLL = 1.8V –40°C to +85°C 18.75 ns
tSU_SPI Set Up Time Data to Clock SPI VLL = 5V –40°C to +85°C 1.0 ns
tSU_SPI Set Up Time Data to Clock SPI VLL = 3.3V –40°C to +85°C 2 ns
tSU_SPI Set Up Time Data to Clock SPI VLL = 1.8V –40°C to +85°C 5 ns
tH_SPI Hold Time Data to Clock SPI VLL = 5V –40°C to +85°C 1.0 ns
tH_SPI Hold Time Data to Clock SPI VLL = 3.3V –40°C to +85°C 1.2 ns
tH_SPI Hold Time Data to Clock SPI VLL = 1.8V –40°C to +85°C 3 ns
tDO Clock Delay Time to Data Out VLL = 5V –40°C to +85°C 3 12.8 ns
tDO Clock Delay Time to Data Out VLL = 3.3V –40°C to +85°C 4 16.3 ns
tDO Clock Delay Time to Data Out VLL = 1.8V –40°C to +85°C 7 34 ns
tS/LE Set Up Time Before LE Rises –40°C to +85°C 25 ns
tW/LE Time Width of LE –40°C to +85°C 12 ns
tWCLR Time Width of CLR –40°C to +85°C 55 ns