SLOS942 April   2018 TPA3126D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      TPA3126 and TPA3116 Idle Current
      2.      Simplified Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gain Setting and Master and Slave
      2. 8.3.2  Input Impedance
      3. 8.3.3  Startup and Shutdown Operation
      4. 8.3.4  PLIMIT Operation
      5. 8.3.5  GVDD Supply
      6. 8.3.6  BSPx and BSNx Capacitors
      7. 8.3.7  Differential Inputs
      8. 8.3.8  Device Protection System
      9. 8.3.9  DC Detect Protection
      10. 8.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 8.3.11 Thermal Protection
      12. 8.3.12 Device Modulation Scheme
        1. 8.3.12.1 BD Modulation
      13. 8.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      14. 8.3.14 Ferrite Bead Filter Considerations
      15. 8.3.15 When to Use an Output Filter for EMI Suppression
      16. 8.3.16 AM Avoidance EMI Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mono PBTL Mode
      2. 8.4.2 Mono BTL Mode (Single Channel Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Select the PWM Frequency
          2. 9.1.1.2.2 Select the Amplifier Gain and Master/Slave Mode
          3. 9.1.1.2.3 Select Input Capacitance
          4. 9.1.1.2.4 Select Decoupling Capacitors
          5. 9.1.1.2.5 Select Bootstrap Capacitors
        3. 9.1.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Mode
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Heat Sink Used on the EVM
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Related Documentation
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Input Impedance

The TPA3126D2 input stage is a fully differential input stage and the input impedance changes with the gain setting from 7.3 kΩ at 36 dB gain to 50 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The tolerance of the input resistor value is ±20% so that the minimum value will be higher than 5.9 kΩ. The inputs must be AC-coupled to minimize the output DC-offset and ensure correct ramping of the output voltages during power-ON and power-OFF. The input AC-coupling capacitor along with the input impedance forms a high-pass filter with the following cut-off frequency:

Equation 1. TPA3126D2 EQ2_los708.gif

If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. Table 2 lists the recommended AC-coupling capacitors for each gain setting. If a –3-dB frequency response is accepted at 20 Hz, 10 times lower capacitors (for example, a 1-µF capacitor) can be used.

Table 2. Recommended Input AC-Coupling Capacitors

GAIN INPUT IMPEDANCE INPUT CAPACITANCE HIGH-PASS FILTER
20 dB 50 kΩ 1.5 µF 2.1 Hz
26 dB 25 kΩ 3.3 µF 1.9 Hz
32 dB 12.5 kΩ 5.6 µF 2.3 Hz
36 dB 7.3 kΩ 10 µF 2.2 Hz
TPA3126D2 INPUT_IMPEDANCE_los708.gifFigure 26. Input Impedance

The input capacitors should be a type of low leakage, such as quality electrolytic, tantalum, or ceramic capacitors. If a polarized type is used the positive connection should face the input pins which are biased to 3 Vdc.