SLOS431B March   2004  – February 2015 TPA6120A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current-Feedback Amplifier
      2. 9.3.2 Independent Power Supplies
    4. 9.4 Device Functional Modes
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 High Voltage, High Fidelity DAC + Headphone Amplifier Solution
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Resistor Values
          2. 10.2.1.2.2 Checking For Oscillations And Instability
          3. 10.2.1.2.3 Thermal Considerations
        3. 10.2.1.3 Application Performance Plots
      2. 10.2.2 High Fidelity Smartphone Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Performance Plots
  11. 11Power Supply Recommendations
    1. 11.1 Independent Power Supplies
    2. 11.2 Power Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGY|14
  • DWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

Proper board layout is crucial to getting the maximum performance out of the TPA6120A2.

A ground plane should be used on the board to provide a low inductive ground connection. Having a ground plane underneath traces adds capacitance, so care must be taken when laying out the ground plane on the underside of the board (assuming a 2-layer board). The ground plane is necessary on the bottom for thermal reasons.

Stray capacitance can still make its way onto the sensitive outputs and inputs. Place components as close as possible to the pins and reduce trace lengths. See Figure 21 and Figure 22. Place the feedback resistor and the series output resistor extremely close to the pins. The input resistor should also be placed close to the pin. If the amplifier is to be driven in a noninverting configuration, ground the input close to the device so the current has a short, straight path to the PowerPAD (gnd).

osc_sch_los431.gifFigure 21. Layout That Can Cause Oscillation
red_cap_los431.gifFigure 22. Layout Designed To Reduce Capacitance On Critical Nodes

12.2 Layout Example

This is part of a 4-layer board, where ground, V+, V- are on the bottom and two middle traces, respectively. Key items to note in this layout:

  1. R4 and R3 are the output resistors in the schematic. They are sized as 0603 surface mount resistors instead of 0402 for their thermal capacity, as they will be dissipating heat, depending on the output power.
  2. Traces are kept as short as possible to avoid any capacitance or oscillation issues.
  3. In systems that may be using the DWP package with through hole resistors, it's strongly suggested that the input and output pins and components do not have a ground plane directly beneath them, to avoid stray capacitance.

pcb_layout_image_tpa6120a2_qfp.gifFigure 23. PCB Layout Example
AIP022A_Pcb_RTM_topcopper.gifFigure 24. Example PCB Layout, Top Layer and Silkscreen, Top View
AIP022A_Pcb_RTM_mid2copper.gifFigure 26. Example PCB Layout, Middle-2 Layer and Silkscreen, Top View
AIP022A_Pcb_RTM_mid1copper.gifFigure 25. Example PCB Layout, Middle-1 Layer and Silkscreen, Top View
AIP022A_Pcb_RTM_bottomcopper.gifFigure 27. Example PCB Layout, Bottom Layer and Silkscreen, Top View