SLOS431B March   2004  – February 2015 TPA6120A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current-Feedback Amplifier
      2. 9.3.2 Independent Power Supplies
    4. 9.4 Device Functional Modes
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 High Voltage, High Fidelity DAC + Headphone Amplifier Solution
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Resistor Values
          2. 10.2.1.2.2 Checking For Oscillations And Instability
          3. 10.2.1.2.3 Thermal Considerations
        3. 10.2.1.3 Application Performance Plots
      2. 10.2.2 High Fidelity Smartphone Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Performance Plots
  11. 11Power Supply Recommendations
    1. 11.1 Independent Power Supplies
    2. 11.2 Power Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGY|14
  • DWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, xVCC+ to xVCC- Where x=L or R channel 9 33 V
Input voltage, VI(2) ± VCC
Differential input voltage, VID 6 V
Minimum load impedance 8 Ω
Continuous total power dissipation See Thermal Information
Operating free–air temperature range, TA –40 85 °C
Operating junction temperature range, TJ(3) –40 150 °C
Storage Temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) When the TPA6120A2 is powered down, the input source voltage must be kept below 600mV peak.
(3) The TPA6120A2 incorporates an exposed PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic Discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) For Pins: LVCC+, RVCC+, LVCC-, RVCC ±500 V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all other pins For all pins except: LVCC+, RVCC+, LVCC-, RVCC ±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 ±1500
(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage, VCC+ and VCC- Split Supply ±5 ±15 V
Single Supply 10 30
Load impedance VCC = ±5V or ±15V 16 Ω
Operating free–air temperature, TA –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) TPA6120A2 TPA6120A2 UNIT
DWP [HSOP] RGY [VQFN]
20 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 44.5 49.4 °C/W
RθJCtop Junction-to-case (top) thermal resistance 55.2 62.0
RθJB Junction-to-board thermal resistance 36.1 25.4
ψJT Junction-to-top characterization parameter 23.1 1.6
ψJB Junction-to-board characterization parameter 36.2 25.5
RθJCbot Junction-to-case (bottom) thermal resistance 7.6 6.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VIO| Input offset voltage (measured differentially) VCC = ±5V or ±15V 2 5 mV
PSRR Power supply rejection ratio VCC = ±5V to±15V 75 dB
VIC Common mode input voltage VCC = ±5V ±3.4 ±3.7 V
VCC = ±15V ±13.2 ±13.5
ICC Supply current (each channel) VCC = ±5V 11.5 13 mA
VCC= ±15V 15
IO Output current (per channel) VCC= ±5V to ±15V 700 mA
Input offset voltage drift VCC = ±5V or ±15V 20 µV/°C
ri Input resistance 300 kΩ
ro Output resistance Open Loop 13 Ω
VO Output voltage swing VCC = ±15V, RL = 25Ω 11.8 to -11.5 12.5 to -12.2 V

7.6 Operating Characteristics(1)

TA = 25°C, RL = 25Ω, Gain = 1V/V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THD+N Total harmonic distortion plus noise RL = 32Ω
f = 1kHz		 VCC = ±5V PO = 10mW 101 dB
VCC = ±15V PO = 100mW 90
RL = 64Ω
f = 1kHz		 VCC = ±5V PO = 10mW 104
VCC = ±15V PO = 100mW 94
VCC = ±5V,
Gain = 1V/V		 VO = 3VPP,
RL = 10kΩ
f = 1kHz		 104
VCC = ±15V,
Gain = 1V/V		 VO = 10VPP,
RL = 10kΩ
f = 1kHz		 108
VCC = ±15V,
Gain = 1V/V		 VO = 2VPP,
RL = 10kΩ
f = 1kHz		 112.5
kSVR Supply voltage rejection ratio RL = 32Ω
f = 1kHz
V(RIPPLE) = 1VPP		 VCC= ±5V –75 dB
VCC= ±15V –78
RL = 64Ω
f = 1kHz
V(RIPPLE) = 1VPP		 VCC= ±5V –75
VCC= ±15V –75
CMRR Common mode rejection ratio (differential) VCC = ±5V or ±15V 100 dB
SR Slew rate VCC = ±15V, Gain = 5V/V, VO = 20 VPP 1300 V/µs
VCC = ±5V, Gain = 2V/V, VO = 5 VPP 900
Vn Output noise voltage VCC = ±5V to ±15V
RL = 16Ω		 Gain = 1V/V 0.9 μVrms
SNR Signal-to-noise ratio
RL = 32Ω to 64Ω
f = 1kHz		 VCC = ±15V, Gain = 1V/V. A Weighted 128 dB
VCC = ±5V, Gain = 1V/V. A Weighted 116
Crosstalk VI = 1VRMS
RF = 1kΩ
RL = 32Ω to 64Ω
f = 1kHz		 VCC = ±15V -112 dB
VCC = ±5V -105
(1) For THD+N, kSVR, and crosstalk, the bandwidth of the measurement instruments was set to 80kHz.

7.7 Typical Characteristics

C001_THDvFreq10k_Fig1.png
RL = 10kΩ Gain = 3V/V RF = 2kΩ
RI = 1kΩ BW = 80kHz
Figure 1. Total Harmonic Distortion + Noise versus Frequency
C004_THDvFreq32_Fig4.png
RL = 32Ω Gain = 3V/V RF = 2kΩ
RI = 1kΩ BW = 80kHz
Figure 3. Total Harmonic Distortion + Noise versus Frequency
C007_THDvPo64_Fig7.png
RL = 64Ω Gain = 3V/V RF = 2kΩ
RI = 1kΩ BW = 80kHz f = 1kHz
Figure 5. Total Harmonic Distortion + Noise versus Output Power
C009_PdvsPo_.png
Mono VCC = ±15V
Figure 7. Power Dissipation versus Output Power
C011_kSVRvFreq_15V_Fig11.png
VCC = ±5V V(ripple) = 1VPP Gain = 2V/V
BW = 80kHz
Figure 9. Supply Voltage rejection Ratio versus Frequency
C015_PdvsPo_50mWScale.png
Figure 11. Power Dissipation versus Power Output - 50mW Scale
C003_THDvFreq64_Fig3.png
RL = 64Ω Gain = 3V/V RF = 2kΩ
RI = 1kΩ BW = 80kHz
Figure 2. Total Harmonic Distortion + Noise versus Frequency
C005_THDvPo10k_Fig5.png
RL = 10kΩ Gain = 3V/V RF = 2kΩ
RI = 1kΩ BW = 80kHz f = 1kHz
Figure 4. Total Harmonic Distortion + Noise versus Output Voltage
C008_THDvPo32_Fig8.png
RL = 32Ω Gain = 3V/V RF = 2kΩ
RI = 1kΩ BW = 80kHz f = 1kHz
Figure 6. Total Harmonic distortion + Noise versus Output Power
C009_PdvsPo_.png
VCC = ±12V V(ripple) = 1VPP Gain = 2V/V
BW = 80kHz
Representative of both positive and negative supplies
Figure 8. Power Dissipation versus Total Output Power
C014_XTalkvFreq_Fig14.png
RF = 1kΩ Gain = 2V/V BW = 80kHz
Figure 10. Crosstalk versus Frequency