SLLSEG9C June   2013  – December  2019 TPD2E2U06

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 Level 4
      2. 7.3.2 IO Capacitance
      3. 7.3.3 DC Breakdown Voltage
      4. 7.3.4 Ultra-Low Leakage Current
      5. 7.3.5 Low ESD Clamping Voltage
      6. 7.3.6 Industrial Temperature Range
      7. 7.3.7 Small Easy-to-Route Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 µA 5.5 V
VCLAMP IO to GND IPP = 1 A, TLP(1) 9.7 V
IPP = 5 A, TLP(1) 12.4
VCLAMP GND to IO IPP = 1 A, TLP(1) 1.9 V
IPP = 5 A, TLP(1) 4
RDYN Dynamic resistance DRL package IO to GND(2) 0.5 Ω
RDYN Dynamic resistance DRL package GND to IO(2) 0.25 Ω
RDYN Dynamic resistance DCK package IO to GND(2) 0.6 Ω
RDYN Dynamic resistance DCK package GND to IO(2) 0.4 Ω
CL Line capacitance f = 1 MHz, VBIAS = 2.5 V(3) 1.5 1.9 pF
CCROSS Channel-to-channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins(3) 0.02 0.03 pF
∆CIO-TO-GND Variation of channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V,
channel_x pin to GND – channel_y pin to GND(3) 		0.03 0.1 pF
VBR Break-down voltage IIO = 1 mA 6.5 8.5 V
ILEAK Leakage current VIO = 2.5 V 1 10 nA
(1) Transmission Line Pulse with 10-ns rise time, 100-ns width.
(2) Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A.
(3) Measured at 25°C.