Figure 7-50 I²C Serial Communications GPIO Allocation

When configured to I²C, the following IOs are used by the macro-cell:

• IO6: SCL

• IO7: SDA

• IO5: HW defined ADDR 3, A3 (optional)

• IO4: HW defined ADDR 4, A4 (optional)

• IO3: HW defined ADDR 5, A5 (optional)

• IO2: HW defined ADDR 6, A6 (optional)

The TPLD2001 supports:

• Peripheral/Target mode only

• Standard mode, Fast mode, and Fast mode plus

• Configurable 4-bit hardware address by IO or by OTP memory

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

The target device address of the TPLD is derived from the OTP and the most significant byte have an option to come from IOs, which the TPLD will continuously sample while powered on. There is also an option to enable IO latching to sample the IO only at power up of the TPLD device, which will allow use of the respective GPIO as a digital input within a circuit design.

Figure 7-51 I²C Read/Write Timing Diagram

Figure 7-52 TPLD I²C Frame and Formatting

I²C communication with this device is initiated by a controller sending a START condition, a high-to-low transition on the SDA input/output, while the SCL input is high. After the START condition, the device hardware address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address input of the responder device must not be changed between the START and the STOP conditions.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (START or STOP).

A STOP condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the controller.

Any number of data bytes can be transferred from the transmitter to receiver between the START and the STOP conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a responder receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must generate a NACK after each byte that it receives from the responder transmitter. Setup and hold times must be met for proper operation.

A controller receiver signals an end of data to the responder transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the responder. This is done by the controller receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the controller to generate a STOP condition.

When writing or reading from the TPLD2001, there is an option to enable automatic address incrementing by writing a logic 0 to bit 0 of address 0x0FD. This can be disabled by writing a logic 1. Note, for I²C, the address auto-increment only works within a specific extended, or page, address. Thus, if burst read or write is used, keep in mind 0x0FF will roll over to 0x000.

Figure 7-53 TPLD I²C Write Command Formatting

To transmit data or write to the TPLD2001, the bus controller must send the device hardware address and set the least significant bit (LSB) to a logic 0. The next two bytes set the register address and then the write data follows. There is no limitation on the number of data bytes sent in one write frame.

Figure 7-54 TPLD I²C Read Command Formatting

To read from the TPLD2001, the bus controller first must send the TPLD2001 hardware address with the LSB set to a logic 1. The byte that follows contains the data in the address previously written to, or the next address if address auto-increment is enabled.

Figure 7-55 TPLD I²C Software Reset Command

The Software Reset call is a command sent from the controller on the I2C bus that instructs all devices that support the command to be reset to the power-up default state. In order for it to function as expected, the I²C bus must be functional and no devices can be hanging the bus.

The software Reset call is defined as the following steps:

1. A START condition is sent by the I²C bus controller.

2. The address used is the reserved General Call I²C bus address '0000 000' with the R/W bit set to 0. The byte sent is 0x00.

3. Any devices supporting the General Call functionality will ACK. If the R/W bit is set to 1 (read), the device will NACK.

4. Once the General Call address is acknowledged, the controller sends only 1 byte of data equal to 0x06. If the data byte is any other value, the device will not acknowledge nor reset. If more than 1 byte is sent, no more bytes will be acknowledged and the device will ignore the I²C message considering it invalid.

5. After the 1 byte of data (0x06) is sent, the controller sends a STOP condition to end the Software Reset call sequence. A repeated START condition will be ignored by the device and no reset would be performed.

Once the above steps are completed successfully, the device will perform a reset, clearing all register values back to power-on defaults.