SCPS286 July   2025 TPLD2001

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.3.1 3-Bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-Bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-Bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.5.1 4-Bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing blocks
        1. 7.3.4.1 3-Bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Comparator Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Analog Comparators
        1. 7.3.11.1 Discrete Analog Comparator (ACMP)
        2. 7.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Analog Multiplexer (AMUX)
      15. 7.3.15 Oscillators
        1. 7.3.15.1 2kHz Fixed Frequency Oscillator
        2. 7.3.15.2 2MHz Fixed Frequency Oscillator
        3. 7.3.15.3 25MHz Fixed Frequency Oscillator
        4. 7.3.15.4 Oscillator Power Modes
      16. 7.3.16 Serial Communications
        1. 7.3.16.1 I2C Mode
        2. 7.3.16.2 SPI Mode
        3. 7.3.16.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP)
        3. 7.4.4.3 Intel HEX File Format
        4. 7.4.4.4 TPLD2001 Registers
          1. 7.4.4.4.1 TPLD2001_User Registers
          2. 7.4.4.4.2 TPLD2001_Cfg_0 Registers
          3. 7.4.4.4.3 TPLD2001_Cfg_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Connection Mux

The connection mux is used to create the internal routing for internal functions of the device once it is programmed. The registers are programmed from the one-time programmable memory (OTP).

The output of each functional macro-cell within the TPLD2001 has a specific digital bit code assigned to it that is either set to active “High” or inactive “Low” based on the design that is created. Once the 2048 register bits within the TPLD2001 are programmed a fully custom circuit will be created.

The connection mux has 83 inputs and 157 outputs. Each of the 83 inputs to the connection mux is hard-wired to a particular source macro-cell, including I/O pins, LUTs, analog comparators, other digital resources and VCC and GND. The input to a digital macro-cell uses a 7-bit register to select one of these 83 input lines.

Table 7-2 Connection mux input table

Connection Mux Input

Connection Mux Input Signal

Mux Decode

6

 5 4 3 2 1 0
0 GND 0 0 0 0 0 0 0
1 IN0 DIN 0 0 0 0 0 0 1
2 IO1 DIN / VIRTUAL IN0 0 0 0 0 0 1 0
3 IO2 DIN / VIRTUAL IN1 0 0 0 0 0 1 1
4 IO3 DIN / VIRTUAL IN2 0 0 0 0 1 0 0
5 IO4 DIN / VIRTUAL IN3 0 0 0 0 1 0 1
6 IO5 DIN / VIRTUAL IN4 0 0 0 0 1 1 0
7 IO6 DIN / VIRTUAL IN5 0 0 0 0 1 1 1
8 IO7 DIN / VIRTUAL IN6 0 0 0 1 0 0 0
9 IO8 DIN / VIRTUAL IN7 0 0 0 1 0 0 1
10 IO9 DIN 0 0 0 1 0 1 0
11 IO10 DIN 0 0 0 1 0 1 1
12 IO11 DIN 0 0 0 1 1 0 0
13 IO12 DIN 0 0 0 1 1 0 1
14 IO13 DIN 0 0 0 1 1 1 0
15 IO14 DIN 0 0 0 1 1 1 1
16 IO15 DIN 0 0 1 0 0 0 0
17 IO16 DIN 0 0 1 0 0 0 1
18 IO17 DIN 0 0 1 0 0 1 0
19 LUT2_0 / DFF OUT 0 0 1 0 0 1 1
20 LUT2_1 / DFF OUT 0 0 1 0 1 0 0
21 LUT2_2 / DFF OUT 0 0 1 0 1 0 1
22 LUT2_3 / PGEN OUT 0 0 1 0 1 1 0
23 LUT3_0 / DFF OUT 0 0 1 0 1 1 1
24 LUT3_1 / DFF OUT 0 0 1 1 0 0 0
25 LUT3_2 / DFF / SR OUT 0 0 1 1 0 0 1
26 LUT3_3 / DFF / SR OUT 0 0 1 1 0 1 0
27 LUT3_4 / DFF / SR OUT 0 0 1 1 0 1 1
28 LUT3_5 / DFF / SR OUT 0 0 1 1 1 0 0
29 LUT3_6 / LDC OUT 0 0 1 1 1 0 1
30 LUT3_7 / LDC OUT 0 0 1 1 1 1 0
31 LUT3_8 / LDC OUT 0 0 1 1 1 1 1
32 LUT3_9 / LDC OUT 0 1 0 0 0 0 0
33 LUT3_10 / LDC OUT 0 1 0 0 0 0 1
34 LUT3_11 / LDC OUT 0 1 0 0 0 1 0
35 LUT4_0 / DFF OUT 0 1 0 0 0 1 1
36 LUT4_1 / DFF OUT 0 1 0 0 1 0 0
37 LUT4_2 / DFF OUT 0 1 0 0 1 0 1
38 LUT4_3 / DFF OUT 0 1 0 0 1 1 0
39 PFLT0 OUT 0 1 0 0 1 1 1
40 PFLT1 OUT 0 1 0 1 0 0 0
41 FLT / EDET OUT 0 1 0 1 0 0 1
42 SM OUT0 0 1 0 1 0 1 0
43 SM OUT1 0 1 0 1 0 1 1
44 SM OUT2 0 1 0 1 1 0 0
45 SM OUT3 0 1 0 1 1 0 1
46 SM OUT4 0 1 0 1 1 1 0
47 SM OUT5 0 1 0 1 1 1 1
48 SM OUT6 0 1 1 0 0 0 0
49 SM OUT7 0 1 1 0 0 0 1
50 ACMP0 OUT 0 1 1 0 0 1 0
51 ACMP1 OUT 0 1 1 0 0 1 1
52 ACMP2 OUT 0 1 1 0 1 0 0
53 ACMP3 OUT 0 1 1 0 1 0 1
54 McACMP CH0_0 OUT 0 1 1 0 1 1 0
55 McACMP CH0_1 OUT 0 1 1 0 1 1 1
56 McACMP CH1_0 OUT 0 1 1 1 0 0 0
57 McACMP CH1_1 OUT 0 1 1 1 0 0 1
58 McACMP CH2_0 OUT 0 1 1 1 0 1 0
59 McACMP CH2_1 OUT 0 1 1 1 0 1 1
60 McACMP CH3_0 OUT 0 1 1 1 1 0 0
61 McACMP CH3_1 OUT 0 1 1 1 1 0 1
62 McACMP DATA RDY 0 1 1 1 1 1 0
63 OSC0 OUT0 0 1 1 1 1 1 1
64 OSC0 OUT1 1 0 0 0 0 0 0
65 OSC1 OUT0 1 0 0 0 0 0 1
66 OSC1 OUT1 1 0 0 0 0 1 0
67 OSC2 OUT 1 0 0 0 0 1 1
68 CNT8 OUT 1 0 0 0 1 0 0
69 CNT9 OUT 1 0 0 0 1 0 1
70 CNT10 OUT 1 0 0 0 1 1 0
71 CNT11 OUT 1 0 0 0 1 1 1
72 PWM GEN0 OUTP 1 0 0 1 0 0 0
73 PWM GEN0 OUTN 1 0 0 1 0 0 1
74 PWM GEN1 OUTP 1 0 0 1 0 1 0
75 PWM GEN1 OUTN 1 0 0 1 0 1 1
76 PWM GEN2 OUTP 1 0 0 1 1 0 0
77 PWM GEN2 OUTN 1 0 0 1 1 0 1
78 PWM GEN3 OUTP 1 0 0 1 1 1 0
79 PWM GEN3 OUTN 1 0 0 1 1 1 1
80 WDT OUT 1 0 1 0 0 0 0
81 Reserved1 1 0 1 0 0 0 1

...

...

...

...

...

...

...

...

...
125 Reserved1 1 1 1 1 1 0 1
126 POR OUT 1 1 1 1 1 1 0
127 VCC 1 1 1 1 1 1 1

  1. Reserved options are internally connected to VCC.

Table 7-3 Connection mux output table

Connection mux output

Connection mux output signal
0 IO1 DOUT
1 IO1 OE
2 IO2 DOUT
3 IO2 OE
4 IO3 DOUT
5 IO3 OE
6 IO4 DOUT
7 IO5 DOUT
8 IO6 DOUT
9 IO7 DOUT
10 IO8 DOUT
11 IO9 DOUT
12 IO10 DOUT
13 IO10 OE
14 IO11 DOUT
15 IO11 OE
16 IO12 DOUT
17 IO12 OE
18 IO13 DOUT
19 IO13 OE
20 IO14 DOUT
21 IO15 DOUT
22 IO15 OE
23 IO16 DOUT
24 IO16 OE
25 IO17 DOUT
26 IO17 OE
27 LUT2_0 IN0 / DFF CLK IN
28 LUT2_0 IN1 / DFF D IN
29 LUT2_1 IN0 / DFF CLK IN
30 LUT2_1 IN1 / DFF D IN
31 LUT2_2 IN0 / DFF CLK IN
32 LUT2_2 IN1 / DFF D IN
33 LUT2_3 IN0 / PGEN CLK IN
34 LUT2_3 IN1 / PGEN RST IN
35 LUT3_0 IN0 / DFF CLK IN
36 LUT3_0 IN1 / DFF D IN
37 LUT3_0 IN2 / DFF RST IN
38 LUT3_1 IN0 / DFF CLK IN
39 LUT3_1 IN1 / DFF D IN
40 LUT3_1 IN2 / DFF RST IN
41 LUT3_2 IN0 / DFF / SR CLK IN
42 LUT3_2 IN1 / DFF / SR D IN
43 LUT3_2 IN2 / DFF / SR RST IN
44 LUT3_3 IN0 / DFF / SR CLK IN
45 LUT3_3 IN1 / DFF / SR D IN
46 LUT3_3 IN2 / DFF / SR RST IN
47 LUT3_4 IN0 / DFF / SR CLK IN
48 LUT3_4 IN1 / DFF / SR D IN
49 LUT3_4 IN2 / DFF / SR RST IN
50 LUT3_5 IN0 / DFF / SR CLK IN
51 LUT3_5 IN1 / DFF / SR D IN
52 LUT3_5 IN2 / DFF / SR RST IN
53 LUT3_6 IN0 / DFF CLK IN OR LDC IN0
54 LUT3_6 IN1 / DFF D IN OR LDC IN1
55 LUT3_6 IN2 / DFF RST IN OR LDC IN2
56 LUT3_7 IN0 / DFF CLK IN OR LDC IN0
57 LUT3_7 IN1 / DFF D IN OR LDC IN1
58 LUT3_7 IN2 / DFF RST IN OR LDC IN2
59 LUT3_8 IN0 / DFF CLK IN OR LDC IN0
60 LUT3_8 IN1 / DFF D IN OR LDC IN1
61 LUT3_8 IN2 / DFF RST IN OR LDC IN2
62 LUT3_9 IN0 / DFF CLK IN OR LDC IN0
63 LUT3_9 IN1 / DFF D IN OR LDC IN1
64 LUT3_9 IN2 / DFF RST IN OR LDC IN2
65 LUT3_10 IN0 / DFF CLK IN OR LDC IN0
66 LUT3_10 IN1 / DFF D IN OR LDC IN1
67 LUT3_10 IN2 / DFF RST IN OR LDC IN2
68 LUT3_11 IN0 / DFF CLK IN OR LDC IN0
69 LUT3_11 IN1 / DFF D IN OR LDC IN1
70 LUT3_11 IN2 / DFF RST IN OR LDC IN2
71 LUT4_0 IN0 / DFF CLK IN
72 LUT4_0 IN1 / DFF D IN
73 LUT4_0 IN2 / DFF RST IN
74 LUT4_0 IN3
75 LUT4_1 IN0 / DFF CLK IN
76 LUT4_1 IN1 / DFF D IN
77 LUT4_1 IN2 / DFF RST IN
78 LUT4_1 IN3
79 LUT4_2 IN0 / DFF CLK IN
80 LUT4_2 IN1 / DFF D IN
81 LUT4_2 IN2 / DFF RST IN
82 LUT4_2 IN3
83 LUT4_3 IN0 / DFF CLK IN
84 LUT4_3 IN1 / DFF D IN
85 LUT4_3 IN2 / DFF RST IN
86 LUT4_3 IN3
87 PFLT0 IN
88 PFLT1 IN
89 FLT / EDET IN
90 SM ST0 EN0
91 SM ST0 EN1
92 SM ST0 EN2
93 SM ST1 EN0
94 SM ST1 EN1
95 SM ST1 EN2
96 SM ST2 EN0
97 SM ST2 EN1
98 SM ST2 EN2
99 SM ST3 EN0
100 SM ST3 EN1
101 SM ST3 EN2
102 SM ST4 EN0
103 SM ST4 EN1
104 SM ST4 EN2
105 SM ST5 EN0
106 SM ST5 EN1
107 SM ST5 EN2
108 SM ST6 EN0
109 SM ST6 EN1
110 SM ST6 EN2
111 SM ST7 EN0
112 SM ST7 EN1
113 SM ST7 EN2
114 SM CLK IN
115 SM RST IN
116 ACMP0 PWR UP
117 ACMP1 PWR UP
118 ACMP2 PWR UP
119 ACMP3 PWR UP
120 McACMP ENABLE
121 McACMP RST
122 OSC0 PWR DOWN
123 OSC1 PWR DOWN
124 OSC2 PWR DOWN
125 CNT6 / FSM IN
126 CNT6 / FSM UP
127 CNT6 / FSM KEEP
128 CNT6 / FSM CLK IN
129 CNT7 / FSM IN
130 CNT7 / FSM UP
131 CNT7 / FSM KEEP
132 CNT7 / FSM CLK IN
133 CNT8 / FSM IN
134 CNT8 / FSM UP
135 CNT8 / FSM KEEP
136 CNT8 / FSM CLK IN
137 CNT9 / FSM IN
138 CNT9 / FSM UP
139 CNT9 / FSM KEEP
140 CNT9 / FSM CLK IN
141 PWM GEN0 PWR UP
142 PWM GEN1 PWR UP
143 PWM GEN2 PWR UP
144 PWM GEN3 PWR UP
145 WDT EN
146 WDT IN
147 VIRTUAL OUT0
148 VIRTUAL OUT1
149 VIRTUAL OUT2
150 VIRTUAL OUT3
151 VIRTUAL OUT4
152 VIRTUAL OUT5
153 VIRTUAL OUT6
154 VIRTUAL OUT7
155 AMUX0_SEL
156 AMUX1_SEL