SLVSHA3 March   2024 TPS22996H-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ON and OFF Control
      2. 7.3.2 Input Capacitor (Optional)
      3. 7.3.3 Output Capacitor (Optional)
      4. 7.3.4 Quick Output Discharge
      5. 7.3.5 Humidity Resistance
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Adjustable Rise Time
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Power Dissipation
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DYC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPS22996H-Q1 is a 5.5V, dual-channel, 13mΩ (typical) RON load switch in a 8-pin DYC package. Each channel can support a maximum continuous current of 4A and is controlled by an on and off GPIO-compatible input. To reduce the voltage drop in high current rails, the device implements N-channel MOSFETs. Note that the ON pins must be connected and cannot be left floating. The device has a configurable slew rate for applications that require specific rise-time, which controls the inrush current. By controlling the inrush current, power supply sag can be reduced during turnon. Furthermore, the slew rate is proportional to the series resistor used on the ONx pin. See Section 7.3.7 to determine the correct resistor value for a desired rise time.

The internal circuitry is powered by the VBIAS pin, which supports voltages from 2.5V to 5.5V. This circuitry includes the charge pump, QOD, and control logic. When a voltage is applied to VBIAS, and the ON1,2 pins transition to a low state, the QOD functionality is activated. This connects VOUT1 and VOUT2 to ground through the on-chip resistor. The typical pulldown resistance (RPD) is 230Ω.

During the off state, the device prevents downstream circuits from pulling high standby current from the supply. The integrated control logic, driver, power supply, and output discharge FET eliminates the need for any external components, reducing solution size and bill of materials (BOM) count.