8.3.1 Current Limit

The TPS23525 utilizes two current limit thresholds:

• I_CL1 – also referred to as high current limit threshold, which is used when the V_DS of the hot swap FET is low.
• I_CL2 – lower current limit threshold, which is used when the V_DS of the hot swap FET is high.

This dual level protection scheme ensures that the part has a higher chance of riding out voltage steps and other transients due to the higher current limit at low V_DS, while protecting the MOSFET during start into short and hot-short events, by setting a lower current limit threshold for conditions with high V_DS. The transition threshold is programmed with a resistor that is connected from the drain of the hot swap FET to the D pin of the TPS23525. The figure below illustrates an example with a I_CL1 set to 25 A and I_CL2 set to 3 A. Note that compared to a traditional SOA protection scheme this approach allows better utilization of the SOA in the 10 V < V_DS. < 40-V range, which is critical in riding through transients and voltage steps.

Note that in both cases the TPS23525 regulated the gate voltage to enforce the current limit. However, this regulation is not very fast and doesn’t offer the best protection against hot-shorts on the output. To protect in this scenario a fast comparator is used, which quickly pulls down the gate in case of severe over current events (2x bigger than V_CL1).

8.3.2 Soft Start Disconnect

The inrush current into the output capacitor (C_OUT) can be limited by placing a capacitor between the SS (Soft Start) pin and the drain of the hot swap MOSFET. In that case the inrush current can be computed using equation below.

Note that with most hot swap the C_SS pin is tied simply to the gate pin, but this can interfere with performance during normal operation if transients or short circuits are encountered. In addition the C_SS capacitor tends to pull up the gate during hot plug and cause shoot through current if it is always tied to the gate. For that reason the TPS23525 has a disconnect switch between the gate pin and the SS pin as well as a discharge resistor. During the initial hot plug and during the insertion delay the switch between SS and GATE is open and SS is being discharged to GND through a resistor. Then during start-up SS and GATE are connected to limit the slew rate. Once in normal operation the SS pin is not tied to GATE and it is not shorted to GND, which prevents it from interfering with the operation during transients.

8.3.3 Timer

Timer is a critical feature in the hot swap, which manages the stress level in the MOSFET. The timer will source and sink current into the timer capacitor as follows:

• Not in current limit: sink 2 µA
• If the part is in current limit and V_GATE < V_GATE,TH, the timer sources current as follows:
  • V_D < V_{D,CL_SW}: source 10 µA
  • V_D > V_{D,CL_SW}: source 50 µA

The TPS23525 times out and shuts down the hot swap as follows.

• If V_D < V_{D,TMR_SW} then the hot swap times out when V_TMR reaches 1.5 V.
• If V_D > V_{D,TMR_SW} then the hot swap times out when V_TMR reaches 0.75 V.

The above behavior maximizes the ability of the hot swap to ride out voltage steps, while ensuring that the FET remains safe even if the part can not ride out a voltage step.

A cool down period follows after the part times out. During this time the timer performs the following:

• Discharge C_TMR with a 2-µA current source until 0.5 V
• Charge C_TMR with a 10-µA current source until it is back to 1.5 V.
• Repeat the above 64 times
• Discharge timer to 0 V.

The part attempts to restart after finishing the above. If the UVEN signal is toggled while the 64 cycles are in progress the part restarts immediately after the 64 cycles are completed.

The timer operates as follows when recovering from POR:

• If V_TMR < 0.5 V:
  • Proceed to regular startup
  • Do not discharge V_TMR
• If V_TMR > 0.5 V:
  • Go through 64 charge/discharge cycles
  • Discharge V_TMR
  • Proceed to startup

The Time Out (T_TO) can be computed using the equations below. Note that the time out depends on the V_DS of the MOSFET.

8.3.4 OR-ing

The TPS23525 features integrated OR-ing that controls the external MOSFET in a way to emulate an ideal diode. The TPS23525 will regulate the forward drop across the OR-ing FET to 25 mV. This is accomplished by controlling the V_GS of the MOSFET. As the current decreases the V_GS is also decreased, which effectively increases the R_DSON of the MOSFET. This process is regulated with a low gain amplifier that is gate (OR-ing FET) pole compensated. The lower gain helps ensure stability over various operating conditions. The regulating amplifier ensures that there is no DC reverse current.

However, the amplifier is not very fast and thus it is paired with a fast comparator. This comparator quickly turns off the FET if there is significant reverse current detected.

8.4.1 OFF State

In this state the hot swap FET is turned off and the controller is waiting to start-up. The controller can be in this state due to any of these scenarios:

• Input voltage is not in the valid range.
• The hot swap is in the cool down state and the timer is going through the retry cycle after a fault condition such as output hot short or over current.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

8.4.2 Insertion Delay State

In this state the hot swap FET is turned off and the controller is waiting for the insertion delay to finish. This allows the input supply to settle after a Hot Plug. If any of the following occur, the controller will be kicked back to the OFF state:

• Input voltage is not in the valid range.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

Once the insertion delay is finished, the controller will move to the Start-up state.

8.4.3 Start-up State

In this state the controller is turning on and charging the output cap. The operation is set as follows:

• The SS pin is internally connected to the GATE pin to allow for output dv/dt control.
• Lower gate sourcing current is applied to the GATE pin to allow for smaller SS caps.
• The lower current limit setting of V_SNS,CL2 and a lower fast trip setting of V_SNS,FST2 is used to minimize the MOSFET stress in case of a fault condition.

If any of the following occur, the controller will be kicked back to the OFF state:

• Input voltage is not in the valid range.
• The timer times out due to over-current.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
• Fast trip is triggered.

Once the PG_degl signal goes Hi, the controller will move to the Normal Operation state.

8.4.4 Normal Operation State

In this state the hot swap is fully on and the operation is set as follows:

• The SS pin is disconnected from the GATE pin to improve transient response.
• The full gate sourcing current is used to improve transient response.
• The current limit and fast trip threshold are a function of the D pin to optimize the transient response while protecting the MOSFET.

If any of the following occur, the controller will be kicked back to the OFF state:

• • PG_degl goes low.
• The timer times out due to over-current.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

Note that if the input voltage is outside the valid range or the fast trip is triggered, the hot swap FET will turn off, but the controller will not exit the Normal Operation state. In this case the PG signal would go low immediately. If this condition persists, the PG_degl will go low as well and the controller would move to the OFF state. This operation prevents the controller from re-starting the system during quick transients.