SLVSDX0B October   2017  – November 2017 TPS23525

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Relationship between Sense Voltage, Gate Current, and Timer
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
        1. 8.3.1.1 Programming the CL Switch-Over Threshold
        2. 8.3.1.2 Programming CL1
        3. 8.3.1.3 Programming CL2
        4. 8.3.1.4 Computing the Fast Trip Threshold
      2. 8.3.2 Soft Start Disconnect
      3. 8.3.3 Timer
      4. 8.3.4 OR-ing
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF State
      2. 8.4.2 Insertion Delay State
      3. 8.4.3 Start-up State
      4. 8.4.4 Normal Operation State
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting RSNS
        2. 9.2.2.2  Selecting Soft Start Setting: CSS and CSS,VEE
        3. 9.2.2.3  Selecting VDS Switch Over Threshold
        4. 9.2.2.4  Timer Selection
        5. 9.2.2.5  MOSFET Selection and SOA Checks
        6. 9.2.2.6  Input Cap, Input TVS, and OR-ing FET selection
        7. 9.2.2.7  EMI Filter Consideration
        8. 9.2.2.8  Under Voltage and Over Voltage Settings
        9. 9.2.2.9  Choosing RVCC and CVCC
        10. 9.2.2.10 Power Good Interface to Downstream DC/DC
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VVCC (current into VCC <10 mA) –0.3 20 V
Input voltage VSNS, VOV –0.3 6.5 V
VUVEN, VD(1), VSS(1) –0.3 30 V
Input voltage VNeg48A, VNeg48B -0.3 200 V
VNeg48A, VNeg48B through 1-kΩ resistor –2 200 V
Output voltage VGATE, VGATEA, VGATEB –0.3 VCC V
VTMR –0.3 6.5 V
Output voltage VPGb –0.3 200 V
Operating junction temperature, TJ –40 125 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VVCC Supply voltage (current into VCC <10 mA) 0 20 V
VSNS, VOV Input voltage 0 5.5 V
VUVEN, VD(1), VSS(1) Input voltage 0 18 V
VNeg48A, VNeg48B Input voltage, through 1-kΩ resistor –0.2 150 V
VGATE, VGATEA, VGATEB Output voltage 0 VCC V
VTMR Output voltage 0 5.5 V
VPGb Output voltage 0 80 V
CSS Capacitance 1 200 nF
RSS Resistance 1 10 kΩ
RD Resistance 120 2,000 kΩ
RNEG48VA , RNEG48VB Resistance 1 kΩ

6.4 Thermal Information

THERMAL METRIC(1) TPS23525 UNIT
PW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 98.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.3 °C/W
RθJB Junction-to-board thermal resistance 44.3 °C/W
ψJT Junction-to-top characterization parameter 1.8 °C/W
ψJB Junction-to-board characterization parameter 43.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V, –1 V < VNEG48Vx < 150 V, ; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC – Clamped Supply
V(UVLO_VCC) UVLO on VCC rising 9 9.5 10 V
V(UVLO_VCC,hyst) UVLO hysteresis on VCC hysteresis 1 V
V(VCC) VCC regulation 1.1< I(VCC) < 10 mA (current into VCC) 12 14.5 18 V
IQ Quiescent Current VVCC = 10 V. Off 1 mA
VVCC = 10 V. On 1 mA
VVCC = 10 V, Gate, GATEA, GATEB in regulation 1.1 mA
UVEN – Under Voltage and Enable
V(UVEN_T) Threshold voltage for V(UVEN) 0.985 1 1.015 V
I(UV_hyst) Hysteresis current, sourcing from UV pin VUV = 1.5 V 9 10 11.2 µA
OV – Over Voltage
V(OV_T) Threshold voltage for VOV 0.98 1 1.02 V
I(OV_hyst) Hysteresis current, sourcing from OV pin VOV = 1.5 V 9 10 11.2 µA
TMR – Timer
VTMR Voltage on timer when part times out. VD = 0 V, TMR ↑, measure VTMR when VGATE = 0 1.47 1.5 1.53 V
VTMR2 Voltage on timer when part times out. VD = 1 V, TMR ↑, measure VTMR when VGATE = 0 0.735 0.75 0.765 V
ITMR,SRs Timer Sourcing current when in fault condition or when retrying. VSNS = 0.1 V, VD = 0 V, VTMR = 0 V, measure I out from TMR 9 10 11 µA
VSNS = 0.1 V, VD = 2 V, VTMR = 0 V, measure I out from TMR 45 50 55 µA
ITMR,SNC Timer sinking current when not in fault condition. VSNS = 0 V, VD = 0 V, VTMR = 2 V, 1.5 2 2.5 µA
VTMR,RETRY Voltage on timer when the timer starts going back up in retry. Retry version only. VSNS = 0 V, VD = 0 V, TMR ↑ = 2 V, TMR ↓, measure VTMR when I into TMR change polarity 0.475 0.5 0.525 V
NRETRY Number of retry duty cycles. Retry version only. 64
DRETRY Retry duty cycle. Retry version only. 0.4%
IGATE,TIMER Gate Sourcing Current Threshold When timer starts to run. VG = 5 V, VD = 2 V, VSNS ↑, measure IGATE when TMR sources current 5 10 15 µA
VSNS,TMR1 Sense Voltage when Timer starts to run. VD = 2 V, VTMR = 0 V, VG = 5 V; VSNS ↑, measure VSNS when TMR sources current 1.5 2.5 mV
VSNS,TMR2 Sense Voltage when Timer starts to run. VD = 0 V, VTMR = 0 V , VG = 5 V; VSNS ↑, measure VSNS when TMR sources current 23.25 24.5 mV
SNS – Sense Pin For Current Limit
ISNS,LEAK Leakage current on sense pin -2 2 µA
VSNS,CL1 Current limit VTMR = 0 V. VGATE = 5 V. VD = 0 V VSNS ↑, measure when IGATE = 0; 24 25 26 mV
VSNS,FST fast trip current limit VTMR = 0 V. VGATE = 5 V. VD = 0 V. VSNS ↑, measure when IGATE> 100 mA 45 50 55 mV
VSNS,CL2 Fold Back Current Limit VTMR = 0 V, VGATE = 5 V, VD = 5 V, VSNS ↑, measure when IGATE = 0; 2.25 3 3.75 mV
VSNS,FST2 Fast Trip during start-up VTMR = 0 V, VGATE = 5 V, VD = 5 V, VSNS ↑, Measure when IGATE> 100 mA 6 9 12 mV
GATE – Gate Drive for Main Hot Swap FET
V(VCC-GATE) Output gate voltage V(SNS) = 0 V 1 V
I(GATE,SRS,NORM) Sourcing Current during normal operation. V(TMR) = 0 V. V(GATE) = 8 V. VD = 0 V, V(SNS) = 0 V 250 400 µA
I(GATE,SRS,START) Sourcing Current during star-up V(TMR) = 0 V. V(GATE) = 5 V. VD = 0 V, V(SNS) = 0 V 15 20 25 µA
I(GATE,wkpd) Weak pull down current V(SNS) = 0 V. VUVEN = 0 V 3 5 7 mA
I(GATE,FST) Fast Pull down current with 10mV overdrive 0.4 1 1.5 A
D – Drain Sense
R(D,INT) Resistance from the drain pin to GND. 28.5 30 31.5 kΩ
V(D,CL_SW) Voltage on drain that switches between two current limits V(TMR) = 0 V, V(GATE) = 5 V, V(SNS) = 20 mV, D↑, measure V when I(GATE) = 0 1.46 1.5 1.54 V
V(D,TMR_SW) Voltage on drain that switches the VTMR threshold. V(TMR) = 1 V, V(GATE) = 5 V, V(SNS) = 20 mV, D↑, measure V when I(GATE) = 0 0.73 0.75 0.77 V
V(D,TMR_SW,hyst) hysteresis for V(D,TMR,SW) hysteresis 75 mV
SS (Soft Start)
I(SS,PD) Pull down current when not in inrush VSS = 5 V 100 mA
R(SS,GATE) Resistance between GATE and SS in the start-up phase 80 Ω
Neg48A, Neg48B
I(lkg,Neg48x) Leakage current VNeg48x = –50 mV, GATEx ON -2 2 µA
VNeg48x = –100 mV, GATEx ON -7 7 µA
VNeg48x = 150 V, GATEx off 30 µA
V(FWD) Forward regulation voltage of the OR-ing controller. VFWD = VEE – V(NEG48Vx) 10 25 40 mV
V(FWD,FST) Forward voltage where a fast pull up is activated. VGATEx = 5 V. VVEE – VNeg48Vx ↑ measure when IGATEx = 100 µA 50 80 105 mV
V(RV) Fast reverse trip voltage. 2 6 10 mV
GATEA, GATEB
VVCC-GATEx Gate Output Voltage. 0.65 1.1 V
I(GATEx,SRS) Gate sourcing current in regulation VVEE – VNeg48Vx = 50 mV 5 µA
I(GATEx,SINK) Gate sinking current in regulation VVEE – VNeg48Vx = 0 5 µA
RGATE,SRC,FST Pull up resistance in fast sourcing mode. VVEE – VNeg48Vx = 100 mV; Measure current at VGATEx = 0 V. R = VVCC/I 10 kΩ
I(GATEx,FST) Fast Gate pull down current V(VEE) – VNeg48x = –15 mV 0.4 1 1.5 A
PGb (Power Good Bar)
V(GATE,PGb) Threshold on GATE that triggers PGb to assert. Raise VGATE until PGb asserts 6.5 7.25 8 V
V(PGb,PD) Pull down strength on PGb PGb sinking 1 mA 1.5 V
I(PGb,LEAK) leakage current on PGb pin 1 µA
OTSD (Over Temperature Shut Down)
TSD Shutdown temperature Temp Rising 135 155 175 °C
TSD,hyst Shutdown temperature Hysteresis 8 °C

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC – Clamped Supply
tID Insertion Delay VVCC: 0 V → 10 V, measure delay before VGATE ↑ 32 ms
UVEN
TUV,degl Deglitch on UVEN 4 µs
OV
TOV,degl Deglitch on OV 4 µs
SNS
TSNS,FST,RESP Response time to large over current VSNS steps from 0 mV to 60 mV. Measure time for GATE to come down. 300 ns
Neg48VA, NEG48VB
TNeg48Vx,FST,RESP Response time to large reverse current VNEG48Vx steps from -40 mV to 15 mV. Measure time for GATEx to come down. 300 ns
PGb
tPGb,DEGL Deglitch of PGb. (raise GATE, measure delay between GATE and PGb) Power Good ↑ (V(GATE) 0 V → 10 V) Look for PGb ↓ 1 ms
Power Good ↓ (V(GATE) 10 V → 0 V) Look for PGb ↑ 32 ms

6.7 Typical Characteristics

Unless otherwise noted: –40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V, –1 V < VNEG48Vx < 150 V , ;
TPS23525 D001_SLVSDX0.png
Ivcc injected into VCC pin
Figure 1. VCC Regulation Voltage vs Current and Temperature
TPS23525 D003_SLVSDX0.png
Figure 3. Isns Current Vs Temperature
TPS23525 D006_SLVSDX0.png
In Power Good
Figure 5. Vpgb vs Temperature
TPS23525 D002_SLVSDX0.png
VVCC = 10 V, Regulation is current limit
Figure 2. Iq vs Temperature and Operating Condition
TPS23525 D004_SLVSDX0.png
Figure 4. IGATEA vs Temperature
TPS23525 D007_SLVSDX0.png
Figure 6. VVCC-GATE vs Temperature