SLVS933D July 2009 – December 2020 TPS23753A
The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges CIN, CVC, and CVB while the PD is unpowered. Thus VRTN-VDD will be a small voltage just after full voltage is applied to the PD, as seen in Figure 8-3.
The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VDD rises above the UVLO turnon threshold (VUVLO-R, approximately 35 V) with RTN high, the TPS23753A enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-4 for an example. Converter switching is disabled while CIN charges and VRTN falls from VDD to nearly VSS; however, the converter start-up circuit is allowed to charge CVC. Once the inrush current falls about 10% below the inrush current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is permitted.
Converter switching is allowed if the PD is not in inrush and the VC UVLO circuit permits it. Continuing the start-up sequence shown in Figure 8-4, VVC rises as the start-up current source charges CVC and M1 switching is inhibited by the status of the VC UVLO. The VB regulator powers the internal converter circuits as VVC rises. Start-up current is turned off, converter switching is enabled, and a soft-start cycle starts when VVC exceeds UVLO1 (approximately 9 V). VVC falls as it powers both the internal circuits and the switching MOSFET gate. If the converter control-bias output rises to support VVC before it falls to UVLO1 – UVLO1H (approximately 5.5 V), a successful start-up occurs. Figure 8-4 shows a small droop in VVC while the output voltage rises smoothly and a successful start-up occurs.
If VVDD-VSS drops below the lower PoE UVLO (UVLOR – UVLOH, approximately 30.5 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if VVC falls below the converter UVLO (UVLO1 – UVLOH, approximately 5.5 V), the hotswap is in inrush current limit, or 0% duty cycle is demanded by VCTL (VCTL < VZDC, approximately 1.5 V), or the converter is in thermal shutdown.