SLVS885I October 2008 – December 2017 TPS23754 , TPS23754-1 , TPS23756
Refer to the PDF data sheet for device specific package drawings
CTL is the voltage-control loop input to the pulse-width modulator (PWM). Pulling VCTL below VZDC causes GATE to stop switching. Increasing VCTL above VZDC (0 duty cycle voltage) raises the switching MOSFET programmed peak current. The maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The AC gain from CTL to the PWM comparator is 0.5. The internal divider from CTL to ARTN is approximately 100 kΩ.
Use VB as a pullup source for CTL.