SLVS885I October   2008  – December 2017 TPS23754 , TPS23754-1 , TPS23756


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      High-Efficiency Converter Using TPS23754
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD
      2. 7.3.2  BLNK
      3. 7.3.3  CLS
      4. 7.3.4  Current Sense (CS)
      5. 7.3.5  Control (CTL)
      6. 7.3.6  Detection and Enable (DEN)
      7. 7.3.7  DT
      8. 7.3.8  Frequency and Synchronization (FRS)
      9. 7.3.9  GATE
      10. 7.3.10 GAT2
      11. 7.3.11 PPD
      12. 7.3.12 RTN, ARTN, COM
      13. 7.3.13 T2P
      14. 7.3.14 VB
      15. 7.3.15 VC
      16. 7.3.16 VDD
      17. 7.3.17 VDD1
      18. 7.3.18 VSS
      19. 7.3.19 PowerPAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1.  Threshold Voltages
        2.  PoE Start-Up Sequence
        3.  Detection
        4.  Hardware Classification
        5.  Inrush and Start-Up
        6.  Maintain Power Signature
        7.  Start-Up and Converter Operation
        8.  PD Hotswap Operation
        9.  Converter Controller Features
        10. Bootstrap Topology
        11. Current Slope Compensation and Current Limit
        12. Blanking – RBLNK
        13. Dead Time
        14. FRS and Synchronization
        15. T2P, Start-Up, and Power Management
        16. Thermal Shutdown
        17. Adapter ORing
        18. PPD ORing Features
        19. Using DEN to Disable PoE
        20. ORing Challenges
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Input Bridges and Schottky Diodes
        2.  Protection, D1
        3.  Capacitor, C1
        4.  Detection Resistor, RDEN
        5.  Classification Resistor, RCLS
        6.  Dead Time Resistor, RDT
        7.  Switching Transformer Considerations and RVC
        8.  Special Switching MOSFET Considerations
        9.  Thermal Considerations and OTSD
        10. APD Pin Divider Network, RAPD1, RAPD2
        11. PPD Pin Divider Network, RPPD1, RPPD2
        12. Setting Frequency (RFRS) and Synchronization
        13. Current Slope Compensation
        14. Blanking Period, RBLNK
        15. Estimating Bias Supply Requirements and CVC
        16. T2P Pin Interface
        17. Advanced ORing Techniques
        18. Soft Start
        19. Frequency Dithering for Conducted Emissions Control
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 ESD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

PoE Overview

The IEEE 802.3at standard defines a method of safely powering a PD over a cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as detection. The low-power levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE my inquire how much power the PD requires; this is referred to as classification. The PSE may then power the PD if it has adequate capacity.

Type 2 PSEs are required to do type 1 hardware classification, plus a (new) data-layer classification, or an enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. The PD may return the default, 13W current-encoded class, or one of four other choices. DLL classification occurs after power-on and the ethernet data link has been established.

Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 20 shows the operational states as a function of PD input voltage. The upper half is for IEEE 802.3-2008, and the lower half shows specific differences for IEEE 802.3at. The dashed lines in the lower half indicate these are the same (for example, Detect and Class) for both.

TPS23754 TPS23754-1 TPS23756 hi_pwr_dev_lvs885.gifFigure 20. Operational States for PD

The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops and operating margin. The standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation. IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA-568) that may have had AWG 26 conductors. IEEE 802.3at type 2 cabling power loss allotments and voltage drops have been adjusted for 12.5-Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568, typically AWG number 24 conductors). Table 2 shows key operational limits broken out for the two revisions of the standard.

The PSE can apply voltage either between the RX and TX pairs (pins 1 to 2 and 3 to 6 for 10baseT or 100baseT), or between the two spare pairs (4 to 5 and 7 to 8). Power application to the same pin combinations in 1000baseT systems is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS23754 specifications.

A compliant type 2 PD has power management requirements not present with a type 1 PD. These requirements include the following:

  1. Must interpret type 2 hardware classification
  2. Must present hardware class 4
  3. Must implement DLL negotiation
  4. Must behave like a type 1 PD during inrush and start-up
  5. Must not draw more than 13 W for 80 ms after PSE applies operating voltage (power up)
  6. Must not draw more than 13 W if it has not received a type 2 hardware classification or received permission through DLL
  7. Must meet various operating and transient templates
  8. Optionally monitor for the presence or absence of an adapter (assume high power)

As a result of these requirements, the PD must be able to dynamically control its loading and monitor T2P for changes. In cases where the design must know specifically if an adapter is plugged in and operational, the adapter should be individually monitored, typically with an optocoupler.