The TPS23754 drives DEN to VSS whenever VVDD-VVSS is below the lower classification threshold. When the input voltage rises above VCL-ON, the DEN pin goes to an open-drain condition to conserve power. While in detection, RTN is high impedance, and almost all the internal circuits are disabled. An RDEN of 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance ( ΔV / ΔI ) from 23.7 kΩ to 26.3 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the parallel combination of RDEN and internal VDD loading. The input diode bridge’s incremental resistance may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is partially cancelled by the TPS23754's effective resistance during detection.
The type 2 hardware classification protocol of IEEE 802.3at specifies that a type 2 PSE drops its output voltage into the detection range during the classification sequence. The PD is required to have an incorrect detection signature in this condition, which is referred to as the mark event (see Figure 22). After the first mark event, the TPS23754 will present a signature less than 12 kΩ until it has experienced a VVDD-VVSS voltage below the mark reset (VMSR). This is explained more fully in Hardware Classification.