SLVSDJ5D August   2016  – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Implementations in DFP Host Ports
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  9.3.2 VCONN Supply (VCONN, CC1, CC2)
      3. 8.3.3  USB Power Delivery BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB Power Delivery BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Drivers
        1. 8.3.8.1 GDNG, GDNS
        2. 8.3.8.2 G5V
        3. 8.3.8.3 GDPG
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2)
      11. 8.3.11 Sink Attachment Indicator (UFP, DVDD)
      12. 8.3.12 Accessory Attachment Indicator (AUDIO, DEBUG)
      13. 8.3.13 Plug Polarity Indication (POL)
      14. 8.3.14 Power Supplies (VAUX, VDD, VPWR, DVDD)
      15. 8.3.15 Grounds (AGND, GND)
      16. 8.3.16 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (RFBL1 and RFBL2)
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG CSLEW
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 A/C Multiplexing Power Source
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 A/C Power Source (Wall Adapter)
      2. 9.3.2 Dual-Port Power Managed A/C Power Source (Wall Adapter)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VCONN
    3. 10.3 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
      2. 11.1.2 Power Pin Bypass Capacitors
      3. 11.1.3 Supporting Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Discharging after a Fault (VPWR)

There are two types of faults that cause the TPS25741 or TPS25741A to begin a full discharge of VBUS: Slow-shutdown faults and fast-shutdown faults. When a slow-shutdown fault occurs, the device does not disable GDNG until after VBUS is measured below VSOVP (for 5 V contract). When a fast-shutdown fault occurs, the device disables GDNG immediately and then discharges the connector side of the power-path. In both cases, the bleed discharge is applied to the DSCG pin and ISUPP is drawn from the VPWR pin.

Slow-shutdown faults that do not include transmitting a hard reset:

  • Receiving a Hard Reset signal (25 ms < tShutdownDelay < 35 ms)
  • Cable is unplugged (tShutdownDelay < 20 µs)

Slow-shutdown faults that include transmitting hard reset (25 ms < tShutdownDelay < 35 ms)

  • TJ exceeds TJ1 (an overtemperature event)
  • Low voltage alarm occurring outside of a voltage transition
  • High voltage alarm occurring outside of a voltage transition (but not high enough to cause OVP)
  • Receiving an unexpected message during a voltage transition
  • Failure of power supply to transition voltages within required time of 600 ms (tPSTransition [refer to USB Power Delivery in Documentation Support]).
  • A Soft Reset USB Power Delivery message is not acknowledged or Accepted (as required per USB Power Delivery in Documentation Support).
  • A Request USB Power Delivery message is not received in the required time (as required per USB Power Delivery in Documentation Support).
  • Failure to discharge down to 0.725 V after a fault of any kind.

Fast-shutdown faults (hard reset always sent):

  • Fast OVP event occurring at any time.
  • OCP event occurring at any time starting from the transmission of the first USB Power Delivery message.
    • VBUS falling below VBUS_FTH is treated as an OVP event.
  • GD falling edge

The DSCG pin is used to discharge the supply line after a slow-shutdown fault occurs. Figure 32 illustrates the signals involved. Depending on the specific slow-shutdown fault the time tShutdownDelay in Figure 32 is different as indicated in the list above. If the slow-shutdown fault triggers a hard reset, it is sent at the beginning of the tShutdownDelay period. However, the device behavior after the time tShutdownDelay is the same for all slow-shutdown faults. After the tShutdownDelay period, the device sets CTL1 and CTL2 to select 5 V from the power supply and puts the DSCG pin into its ON state (Full Discharge). This discharging continues until the voltage on the VBUS pin reaches VSOPV (for 5 V contract). The device then disables GDNG and again puts the DSCG pin into its ON state. This discharging state lasts until the voltage on VBUS reaches 0.725 V (nominal). If the discharge does not complete within 650 ms, then the device sends a Hard Reset signal and the process repeats. In Figure 32, the times labeled as T20->5 and T5->0 can vary, they depend on the size of the capacitance to be discharged and the size of the external resistor between the DSCG pin and VBUS. The time labeled as TS is a function of how quickly the NFET opens.

TPS25741 TPS25741A Slow_shut_VBUS_slvsdj5.gifFigure 32. Illustration of Slow-Shutdown VBUS Discharge

Figure 33 illustrates a similar discharge procedure for fast-shutdown faults. The main difference from Figure 32 is that the NFET is opened immediately. It is assumed for the purposes of this illustration that the power supply output capacitance (that is, CSOURCE in the reference schematics shown in Figure 20 and Figure 21) is not discharged by the power supply itself, but the VPWR pin is bleeding current from that capacitance. The VPWR pin then draws ISUPP after GDNG disables the external NFET. So, as shown in the figure, the VPWR voltage discharges slowly, while the VBUS pin is discharged quickly once the full discharge is enabled. If the voltage on the VPWR pin takes longer than T20->5 + T5->0 + 0.765s to discharge below VFOVP, then it causes an OVP event and the process repeats.

TPS25741 TPS25741A Fast_shut_slvsdj5.gifFigure 33. Illustration of Fast-Shutdown Discharge

If the discharge does not complete successfully it is treated as a slow-shutdown fault, and the TPS25741 or TPS25741A repeats the discharge procedure until it does complete successfully. Once the discharge completes successfully as described above (that is, VBUS on connector is below 0.725 V), the device waits for 0.765 s (nominal) before trying to source VBUS again.