SLVSDJ5D August   2016  – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Implementations in DFP Host Ports
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  9.3.2 VCONN Supply (VCONN, CC1, CC2)
      3. 8.3.3  USB Power Delivery BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB Power Delivery BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Drivers
        1. 8.3.8.1 GDNG, GDNS
        2. 8.3.8.2 G5V
        3. 8.3.8.3 GDPG
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2)
      11. 8.3.11 Sink Attachment Indicator (UFP, DVDD)
      12. 8.3.12 Accessory Attachment Indicator (AUDIO, DEBUG)
      13. 8.3.13 Plug Polarity Indication (POL)
      14. 8.3.14 Power Supplies (VAUX, VDD, VPWR, DVDD)
      15. 8.3.15 Grounds (AGND, GND)
      16. 8.3.16 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (RFBL1 and RFBL2)
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG CSLEW
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 A/C Multiplexing Power Source
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 A/C Power Source (Wall Adapter)
      2. 9.3.2 Dual-Port Power Managed A/C Power Source (Wall Adapter)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VCONN
    3. 10.3 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
      2. 11.1.2 Power Pin Bypass Capacitors
      3. 11.1.3 Supporting Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND;EN9V = GND; EN12V = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Voltage Comparator (VBUS)
VBUS_RTH VBUS Threshold (Rising voltage) 4.25 4.45 4.65 V
VBUS_FTH VBUS Threshold (Falling voltage) 3.5 3.7 3.9 V
VBUS Threshold (Hysteresis) 0.75 V
Power Supply (VDD, VPWR)
VDD_TH VDD UVLO threshold Rising voltage 2.8 2.91 2.97 V
Falling voltage 2.8 2.86 2.91
Hysteresis, comes into effect once the rising threshold is crossed. 0.05
VPWR_TH VPWR UVLO threshold Rising voltage 4.2 4.45 4.65 V
Falling voltage 3.5 3.7 3.9
Hysteresis, comes into effect once the rising threshold is crossed. 0.75
Supply current drawn from VDD in sleep mode VPWR = 0 V, VDD = 5 V, CC1 and CC2 pins are open. TJ = 25°C 8.5 µA
VPWR = 0 V, VDD = 3.3 V, CC1 and CC2 pins are open. TJ = 25°C 5.4 µA
VPWR = 0 V, VDD = 5 V,CC1 pin open, CC2 pin tied to GND. TJ = 25°C 93 µA
Supply current drawn from VPWR in sleep mode VPWR = 5 V, VDD = 0 V, CC1 and CC2 pins are open. TJ = 25°C 8 µA
VPWR = 5 V, VDD = 0 V, CC1 pin open, CC2 pin tied to GND. TJ = 25°C 89 µA
ISUPP Typical operating current (from VPWR and VDD) Power Delivery Sourcing active, VBUS = 5 V,
VPWR = 5 V, VDD = 3.3 V		 1 1.8 3 mA
Over/Under Voltage Protection (VBUS)
VFOVP Fast OVP threshold, always enabled 5 V Power Delivery contract 5.8 6.05 6.3 V
12 V Power Delivery contract (TPS25741) 13.2 13.75 14.3 V
20 V Power Delivery contract (TPS25741) 22.1 23.05 24.0 V
9 V Power Delivery contract (TPS25741A) 10.1 10.55 11.0 V
15 V Power Delivery contract (TPS25741A) 16.2 16.95 17.7 V
VSOVP Slow OVP threshold, disabled during voltage transitions. (see Figure 1) 5 V Power Delivery contract 5.5 5.65 5.8 V
12 V Power Delivery contract (TPS25741) 13.1 13.4 13.7 V
20 V Power Delivery contract (TPS25741) 21.5 22.0 22.5 V
9 V Power Delivery contract (TPS25741A) 10 10.2 10.4 V
15 V Power Delivery contract (TPS25741A) 16.3 16.5 17 V
VSUVP UVP threshold, disabled during voltage transitions (see Figure 1) 5 V Power Delivery contract 3.5 3.65 3.8 V
12 V Power Delivery contract (TPS25741) 9.2 9.45 9.7 V
20 V Power Delivery contract (TPS25741) 15.7 16.1 16.5 V
9 V Power Delivery contract (TPS25741A) 6.8 6.95 7.1 V
15 V Power Delivery contract (TPS25741A) 11.7 11.95 12.2 V
VAUX
VVAUX Output voltage 0 ≤ IVAUX ≤ IVAUXEXT 2.875 3.2 4.1 V
VAUX Current limit 1 5 mA
IVAUXEXT External load that may be applied to VAUX. 25 µA
DVDD
VDVDD Output voltage 0 mA ≤ IDVDD ≤ 35 mA, CC1 or CC2 pulled to ground via 5.1 kΩ, or both CC1 and CC2 pulled to ground via 1 kΩ 1.75 1.85 1.95 V
Load Regulation Overshoot from VDVDD, 10-mA minimum,
0.198-µF bypass capacitor		 1.7 2 V
Undershoot from VDVDD, 10-mA minimum,
0.198-µF bypass capacitor		 1.7 2 V
Current limit DVDD tied to GND 40 150 mA
VTX
Output voltage Not transmitting or receiving, 0 to 2 mA external load 1.050 1.125 1.200 V
Current Limit VTX tied to GND 2.5 10 mA
Gate Driver Disable (GD)
VGD_TH Input enable threshold voltage Rising voltage 1.64 1.725 1.81 V
Hysteresis 0.15 V
VGDC Internal clamp voltage IGD = 80 µA 6.5 7.5 8.5 V
RGD Internal pulldown resistance From 0 V to 6 V 3 6 9.5 MΩ
Discharge (DSCG)(1)(2)
VDSCGT ON state (linear) IDSCG = 100 mA 0.15 0.42 1 V
IDSCGT ON state (saturation) VDSCG = 4 V, pulsed testing 220 553 1300 mA
RDSCGB Discharge bleeder While CC1 is pulled down by 5.1 kΩ and CC2 is open, VDSCG = 25 V, compute VDSCG/IDSCG 6.6 8.2 10 kΩ
Leakage current 0 V ≤ VDSCG ≤ 25 V 2 µA
P-ch MOSFET Gate Driver (GDPG)
IGDPG Sinking current (ON) 2 V ≤ VGDPG ≤ 25 V 34 41 48 µA
ILGDPG Leakage current 0 V ≤ VGDPG ≤ 25 V 2 µA
N-ch MOSFET Gate Driver (G5V)
IG5VON Sourcing current 0 V ≤ VG5V ≤ 9 V 6.6 10 µA
VG5VON Sourcing voltage (ON) IG5V ≤ 2 µA 10 16 V
RG5VOFF Sinking strength (OFF) VG5V = 1 V 200 Ω
Sinking strength UVLO (safety) VDD = 1.3 V, VPWR = 0 V, VG5V = 1 V 288 µA
VPWR = 1.3 V, VDD = 0 V, VG5V = 1 V 343 µA
Off-state leakage VG5V = 15V 2 µA
N-ch MOSFET Gate Driver (GDNG,GDNS)
IGDNGON Sourcing current 0 V ≤ VGDNS ≤ 25 V,
0 V ≤ VGDNG – VGDNS ≤ 6 V		 13.2 20 30 µA
VGDNGON Sourcing voltage while enabled (VGDNG – VGDNS) 0 V ≤ VGDNS ≤ 25 V, IGDNGON ≤ 4 µA, VPWR = 0 V 7 12 V
0 V ≤ VGDNS ≤ 25 V, IGDNGON ≤ 4 µA, VDD = 0 V 8.5 12 V
RGDNGOFF Sinking strength while disabled VGDNG – VGDNS= 0.5 V,
0 ≤ VGDNS ≤ 25 V		 150 300 Ω
Sinking strength UVLO (safety) VDD = 1.4 V, VGDNG = 1 V,
VGDNS = 0 V, VPWR = 0 V		 145 µA
VDD = 1.4 V, VGDNG = 1 V,
VGDNS = 0 V, VDD = 0 V		 145 µA
Off-state leakage VGDNS = 25 V, VGDNG open 7 µA
Power Control Input (PCTRL)
VPCTRL_TH Active threshold voltage(3) Voltage rising 1.65 1.75 1.85 V
Hysteresis 100 mV
Input resistance 0 V ≤ VPCTRL ≤ VVAUX 1.5 2.9 6 MΩ
Voltage Select (HIPWR), Power Select (PSEL)(4)
Leakage current 0 V ≤ VHIPWR ≤ VDVDD,
0 V ≤ VPSEL ≤ VDVDD		 –1 1 µA
Port Status and Voltage Control (CTL1, CTL2, UFP, POL, DEBUG)(5)
VOL Output low voltage IOL = 4 mA sinking 0.4 V
Leakage Current (6) In Hi-Z state, 0 ≤ VCTLx ≤ 5.5 V or
0 ≤ VUFP ≤ 5.5V		 –0.5 0.5 µA
Presence of Audio Accessory (AUDIO)(13)
IAUD Current pull down VAUDIO = 1 V 34 40 46 kΩ
Leakage current 0 V ≤ VAUDIO ≤ 5.5 V 2 µA
Enable 9 V, 12 V Capability (EN9V, EN12V)(7)
VILGIO Input low threshold voltage 0.585 V
VIHGIO Input high threshold voltage 1.225 V
Input hysteresis 0.25 V
Transmitter Specifications (CC1, CC2)
RTX Output resistance (zDriver, refer to USB Power Delivery in Documentation Support) During transmission 33 48 75 Ω
VTXHI Transmit high voltage External Loading per Figure 28 1.05 1.125 1.2 V
VTXLO Transmit low voltage External Loading per Figure 28 –75 75 mV
Receiver Specifications (CC1, CC2)
VRXHI Receive threshold (rising) 800 840 885 mV
VRXLO Receive threshold (falling) 485 525 570 mV
Receive threshold (hysteresis) 315 mV
Amplitude of interference that can be tolerated. Interference is 600 kHz square wave, rising 0 to 100 mV. 100 mV
Interference is 1 MHz sine wave 1 VPP
DFP Specifications (CC1, CC2)
VDSTD Detach threshold when cable is detached while in standard DFP mode. In standard DFP mode(8), voltage rising 1.52 1.585 1.65 V
Hysteresis 0.02 V
VD1p5 Detach threshold when cable is detached. In 1.5 A DFP mode(9), voltage rising 1.52 1.585 1.65 V
Hysteresis 0.02 V
VD3p0 Detach threshold when cable is detached In 3 A DFP mode(10), voltage rising 2.50 2.625 2.75 V
Hysteresis 0.05 V
VOCN Unloaded output voltage on CC pin normal mode 2.7 4.35 V
VOCDS VPWR = 0 V (in UVLO) or in sleep mode 1.8 5.5 V
IRPSTD Loaded output current while connected through CCx In standard DFP mode(8), CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)		 64 80 96 µA
IRP1.5 Loaded output current while connected through CCx In 1.5 A DFP mode(9), CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)		 166 180 194 µA
IRP3.0 Loaded output current while connected through CCx In 3 A DFP mode(10), CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)		 304 330 356 µA
VRDSTD Ra, Rd detection threshold (falling) In standard DFP mode(8),
0 V ≤ VCCx ≤ 1.5 V (vRd)		 0.15 0.19 0.23 V
Hysteresis 0.02 V
VRD1.5 Ra, Rd detection threshold (falling) In 1.5 A DFP mode(9), CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)		 0.35 0.39 0.43 V
Hysteresis 0.02 V
VRD3.0 Ra, Rd detection threshold (falling) In 3 A DFP mode(10), CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)		 0.75 0.79 0.83 V
Hysteresis 0.02 V
VWAKE Wake threshold (rising and falling), exit from sleep mode VPWR = 4.65 V , 0 V ≤ VDD ≤ 3 V 1.6 3.0 V
IDSDFP Output current on CCx in sleep mode to detect Ra removal. CCx = 0V, CCy floating 40 73 105 µA
Connector Power Specifications (CC1, CC2, VCONN)(16)
UVLO for VCONN (18) Turn-on, VCONN rising 2.2 2.4 2.6 V
Hysteresis 0.1 V
RDSON Resistance from VCONN to CC1 or CC2(14)(17) 4.75 V ≤ VCONN ≤ 5.5 V
(Fixed Supply mode),
ICCx = 250 mA
–40°C ≤ TJ ≤ 125°C		 300 500 mΩ
4.75 V ≤ VCONN ≤ 5.5 V
(Fixed Supply mode),
ICCx = 250 mA
TJ = 25°C		 300 350 mΩ
IOS Current limit measured on CC1 or CC2(15) 4.75 V ≤ VCONN ≤ 5.5 V
(Fixed Supply mode)		 415 490 562 mA
Fault threshold 1.1×IOS 1.25×IOS mA
Over-Current Protection (ISNS, VBUS)
VITRIP Current trip shunt voltage Specified as VISNS – VBUS. The OCP trip point setting assumes the sense resistor is 5 mΩ
HIPWR: 5 A not enabled 19.2 22.6 mV
HIPWR: 5 A enabled 29 34 mV
OTSD
TJ1 Die Temperature (Analog)(11) TJ ↑ 125 135 145 °C
Hysteresis 10
TJ2 Die Temperature (Analog)(12) TJ ↑ 140 150 163 °C
Hysteresis 10
(1) If TJ1 is perceived to have been exceeded an OTSD occurs and the discharge FET is disabled.
(2) The discharge pull-down is not active in the sleep mode.
(3) When voltage on the PCTRL pin is less than V(PCTRL_TH), the amount of power advertised is reduced by half.
(4) Leaving HIPWR or PSEL open is an undetermined state and leads to unpredictable behavior.
(5) These pins are high-z during a UVLO, reset, or in Sleep condition.
(6) The pins were designed for less leakage, but testing only verifies that the leakage does not exceed 1 µA.
(7) Protection is provided against a voltage greater than VDVDD being applied externally.
(8) Standard DFP mode is active after a USB Type-C sink, debug accessory, or audio accessory is attached until the first USB Power Delivery message is transmitted (after GDNG has been enabled).
(9) 1.5 A DFP mode is active after a USB Power Delivery contract has been negotiated.
(10) 3 A DFP mode is active after GDNG has been enabled until a USB Power Delivery message is received.
(11) When TJ1 trips a hard reset is transmitted and discharge is disabled, but the bleeder discharge is not disabled.
(12) TJ2 trips only when some external heat source drives the temperature up. When it trips the DVDD, and VAUX power outputs are turned off.
(13) AUDIO is high-z during a UVLO, reset, or Device Sleep condition.
(14) Based on 120 mV drop at 250 mA (to deliver more than 1 W at VCONN = 4.75 V).
(15) While providing VCONN power, the CCx output is monitored for faults (overloads). Thermal shutdown is provided with thermal cycling (auto-restart).
(16) VCONN is always applied when a UFP is attached, regardless of whether Ra is detected.
(17) There are requirements for the VCONN voltage supplied to CC1 or CC2 in [1]; customers need to take the RDSON into account when designing to meet those requirements.
(18) The VCONN pin has reverse blocking.