SLVSE57C June   2017  – April 2018 TPS2595


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      TPS25953x Overvoltage Clamp Response Time
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Protection (UVP) and Undervoltage Lockout (UVLO)
      2. 8.3.2 Overvoltage Protection
        1. Overvoltage Lockout (OVLO)
        2. Overvoltage Clamp (OVC)
      3. 8.3.3 Inrush Current, Overcurrent and Short Circuit Protection
        1. Slew Rate and Inrush Current Control (dVdt)
        2. Active Current Limiting
        3. Short Circuit Protection
      4. 8.3.4 Overtemperature Protection (OTP)
      5. 8.3.5 Fault Indication (FLT )
      6. 8.3.6 Quick Output Discharge (QOD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Fault Pin Functional Mode 1: Single Device, Self-Controlled
      2. 8.4.2 Enable and Fault Pin Functional Mode 2: Single Device, Host-Controlled
      3. 8.4.3 Enable and Fault Pin Functional Mode 2: Multiple Devices, Self-Controlled
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Programming the Current-Limit Threshold: RILM Selection
        2. Undervoltage Lockout Set Point
        3. Setting Output Voltage Ramp Time (TdVdT)
          1. Case 1: Start-Up Without Load. Only Output Capacitance COUT Draws Current
          2. Case 2: Start-Up With Load. Output Capacitance COUT and Load Draw Current
      3. 9.2.3 Support Component Selection: CIN
      4. 9.2.4 Application Curves
      5. 9.2.5 Controlled Power Down (Quick Output Discharge) using TPS2595x5
      6. 9.2.6 Overvoltage Lockout using TPS259573
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
      2. 12.1.2 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

  • For all applications, a ceramic decoupling capacitor of 0.01 µF or greater is recommended between the IN terminal and GND terminal. For hot-plug applications, where input power-path inductance is negligible, this capacitor can be eliminated or minimized.
  • The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC. See Figure 68 for a PCB layout example.
  • High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.
  • The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a copper plane or island on the board.
  • Locate the following support components close to their connection pins:
    • RILM
    • CdVdT
    • Resistors for the EN/UVLO (or EN/OVLO) pin
    Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for the RILM and CdVdT components to the device must be as short as possible to reduce parasitic effects on the current limit and soft start timing. These traces must not have any coupling to switching signals on the board.
  • Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads, and it must be physically close to the OUT pins.
  • Obtaining acceptable performance with alternate layout schemes is possible; Layout Example has been shown to produce good results and is intended as a guideline.