SLUS772G MARCH   2008  – June 2020 TPS40210 , TPS40211

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Soft Start
      2. 7.3.2  BP Regulator
      3. 7.3.3  Shutdown (DIS/EN Pin)
      4. 7.3.4  Minimum On-Time and Off-Time Considerations
      5. 7.3.5  Setting the Oscillator Frequency
      6. 7.3.6  Synchronizing the Oscillator
      7. 7.3.7  Current Sense and Overcurrent
      8. 7.3.8  Current Sense and Subharmonic Instability
      9. 7.3.9  Current Sense Filtering
      10. 7.3.10 Control Loop Considerations
      11. 7.3.11 Gate Drive Circuit
      12. 7.3.12 TPS40211
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With DIS/EN Pin
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 12-V to 24-V Nonsynchronous Boost Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH Tools
          2. 8.2.1.2.2  Duty Cycle Estimation
          3. 8.2.1.2.3  Inductor Selection
          4. 8.2.1.2.4  Rectifier Diode Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  Input Capacitor Selection
          7. 8.2.1.2.7  Current Sense and Current Limit
          8. 8.2.1.2.8  Current Sense Filter
          9. 8.2.1.2.9  Switching MOSFET Selection
          10. 8.2.1.2.10 Feedback Divider Resistors
          11. 8.2.1.2.11 Error Amplifier Compensation
          12. 8.2.1.2.12 RC Oscillator
          13. 8.2.1.2.13 Soft-Start Capacitor
          14. 8.2.1.2.14 Regulator Bypass
          15. 8.2.1.2.15 Bill of Materials
        3. 8.2.1.3 Application Curves
      2. 8.2.2 12-V Input, 700-mA LED Driver, Up to 35-V LED String
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Devices
      3. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

TJ = –40°C to 125°C, VDD= 12Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE
VFB Feedback voltage range TPS40210 COMP = FB, 4.5 ≤ VDD ≤ 52 V, TJ = 25°C 693 700 707 mV
TPS40211 COMP=FB, 4.5 ≤ VDD ≤ 52 V, TJ = 25°C 254 260 266
TPS40210 COMP = FB, 4.5 ≤ VDD ≤ 52 V, -40°C ≤ TJ ≤ 125°C 686 700 714
TPS40211 COMP = FB, 4.5 ≤ VDD ≤ 52 V, -40°C ≤ TJ ≤ 125°C 250 260 270
INPUT SUPPLY
VDD Input voltage range 4.5 52 V
IDD Operating current 4.5 ≤ VDD ≤ 52 V, no switching, VDIS < 0.8 1.5 2.5 mA
2.5 ≤ VDIS ≤ 7 V 10 20 μA
VDD < VUVLO(on), VDIS < 0.8 530 μA
UNDERVOLTAGE LOCKOUT
VUVLO(on) Turn on threshold voltage 4.00 4.25 4.50 V
VUVLO(hyst) UVLO hysteresis 140 195 240 mV
OSCILLATOR
fOSC Oscillator frequency range(1) 35 1000 kHz
Oscillator frequency RRC = 182 kΩ, CRC = 330 pF 260 300 340
Frequency line regulation 4.5 ≤ VDD ≤ 52 V -20% 7%
VSLP Slope compensation ramp 520 620 720 mV
PWM
tON(min) Minimum pulse width VDD = 12 V(1) 275 400 ns
VDD = 30 V 90 200
tOFF(min) Minimum off time 170 200
VVLY Valley voltage 1.2 V
SOFT-START
VSS(ofst) Offset voltage from SS pin to error amplifier input 700 mV
RSS(chg) Soft-start charge resistance 320 430 600 kΩ
RSS(dchg) Soft-start discharge resistance 840 1200 1600
ERROR AMPLIFIER
GBWP Unity gain bandwidth product(1) 1.5 3.0 MHz
AOL Open loop gain(1) 60 80 dB
IIB(FB) Input bias current (current out of FB pin) 100 300 nA
ICOMP(src) Output source current VFB = 0.6 V, VCOMP = 1 V 100 250 μA
ICOMP(snk) Output sink current VFB = 1.2 V, VCOMP = 1 V 1.2 2.5 mA
OVERCURRENT PROTECTION
VISNS(oc) Overcurrent detection threshold (at ISNS pin) 4.5 ≤ VDD < 52 V, -40°C ≤ TJ ≤ 125°C 120 150 180 mV
DOC Overcurrent duty cycle(1) 2%
VSS(rst) Overcurrent reset threshold voltage (at SS pin) 100 150 350 mV
TBLNK Leading edge blanking(1) 75 ns
CURRENT SENSE AMPLIFIER
ACS Current sense amplifier gain 4..2 5.6 7.2 V/V
IB(ISNS) Input bias current 1 3 μA
DRIVER
IGDRV(src) Gate driver source current VGDRV = 4 V, TJ = 25°C 375 400 mA
IGDRV(snk) Gate driver sink current VGDRV = 4 V, TJ = 25°C 330 400
LINEAR REGULATOR
VBP Bypass voltage output 0 mA < IBP < 15 mA 7 8 9 V
DISABLE/ENABLE
VDIS(en) Turn-on voltage 0.7 1.3 V
VDIS(hys) Hysteresis voltage 25 130 220 mV
RDIS DIS pin pulldown resistance 0.7 1.1 1.5 MΩ
Ensured by design. Not production tested.